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SCIENCE CHINA Information Sciences, Volume 59, Issue 4: 042407(2016) https://doi.org/10.1007/s11432-015-5398-3

Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process

More info
  • ReceivedJun 16, 2015
  • AcceptedJul 13, 2015
  • PublishedSep 29, 2015

Abstract

A novel, area-efficient transient power-rail electrostatic discharge (ESD) clamp circuit is proposed in this work. Current-mirror capacitors are used to reduce the layout area. Logic threshold voltages of inverters are modified to ensure a fully active on-state for the clamp device in ESD conditions. The proposed circuit reduces the layout area by about 56% compared with a circuit without current-mirror capacitors. Transmission line pulse (TLP) test results based on a 65-nm CMOS process demonstrate that the proposed circuit is an efficient on-chip ESD protection scheme for this process. In addition, the proposed circuit achieves a good immunity to mis-triggering with respect to fast power-up transitions.


Funded by

National Basic Research Program of China(2011CBA00606)


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