SCIENCE CHINA Information Sciences, Volume 59, Issue 4: 042404(2016) https://doi.org/10.1007/s11432-015-5407-6

Ultralow-power high-speed flip-flop based on multimode FinFETs

More info
  • ReceivedMay 11, 2015
  • AcceptedJun 17, 2015
  • PublishedOct 12, 2015


In this paper, we first reconstruct a novel planar static contention-free single-phase-clocked flip-flop (S$^{2}$CFF) based on high-performance fin-type field-effect transistors (FinFETs) to achieve high speed and ultralow power consumption. Benefiting from better control of the conductive channel, the shorted-gate (SG-mode) FinFET flip-flop obtains a persistent reduction of 56.7% in average power consumption as well as a considerable improvement in timing performance at a typical 10% data switching activity, while the low-power (LP-mode) FinFET flip-flop promotes the power reduction to 61.8% without appreciable degradation in speed. However, through further analysis of the simulation results, we have revealed an unnecessary energy loss caused by the redundant leaps of internal nodes at the static input `0', which has a noticeable negative impact on total power consumption at low data switching activity. In order to overcome this defect, a conditional precharge technique is introduced to control the charging path, and we demonstrate that the independent-gate (IG-mode) FinFET is the best option for the added control transistor. The verification results indicate that our optimization reduces the power consumption by more than 50% at low data switching activity with an acceptable area and setup time penalty compared with that of LP-mode FinFET flip-flop.

Funded by

"source" : null , "contract" : "2015CB057201"

R&D project of Shenzhen Government China(JCYJ20140417144423198)

National Natural Science Foundation of China(61306040)

National Basic Research Program of China(973)

R&D project of Shenzhen Government China(JCYJ20140417144423194)

Beijing Natural Science Foundation(4152020)


[1] Chen K T, Fujita T, Hara H, et al. A 77\. Google Scholar

[2] Kawaguchi H, Sakurai T. A reduced clock-swing flip-flop (RCSFF) for 63\. Google Scholar

[3] Alioto M, Consoli E, Palumbo G. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2011, 19: 737-750 CrossRef Google Scholar

[4] Giacomotto C, Nedovic N, Oklobdzija V G. IEEE J Solid-State Circ, 2007, 42: 1392-1404 CrossRef Google Scholar

[5] Furuta J, Hamanaka C, Kobayashi K, et al. A 65 nm bistable cross-coupled dual modular redundancy flip-flop capable of protecting soft errors on the c-element. In: Proceedings of VLSI Circuits Symposium, Honolulu, 2010. 123--144. Google Scholar

[6] Matush B I, Mozdzen T J, Clark L T, et al. IEEE Trans Nucl Sci, 2010, 57: 3588-3595 Google Scholar

[7] Hwang Y T, Lin J F, Sheu M H. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2012, 20: 361-366 CrossRef Google Scholar

[8] Li X Y, Jia S, Liu L M, et al. IEICE Trans Electron, 2012, E95-C: 1125-1127 CrossRef Google Scholar

[9] Kawai N, Takayama S, Masumi J, et al. A fully static topologically-compressed 21-transistor flip-flop with 75\. Google Scholar

[10] Kim Y, Arbor A, Jung W Y, et al. A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications. In: Proceedings of IEEE International Solid-State Circuits Conference, San Francisco, 2014. 466--467. Google Scholar

[11] Choi Y K, Asano K, Lindert N, et al. Ultra-thin body SOI MOSFET for deep-sub-tenth micron era. In: Proceedings of IEEE International Electron Devices Meeting, Washington, 1999. 919--921. Google Scholar

[12] Kedzierski J, Nowak E, Kanarsky T, et al. Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2002. 247--250. Google Scholar

[13] Hisamoto D, Lee W C, Kedzierski J, et al. IEEE Trans Electron Dev, 2000, 47: 2320-2325 CrossRef Google Scholar

[14] King T J. FinFETs for nanoscale CMOS digital integrated circuits. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, San Jose, 2005. 207--210. Google Scholar

[15] Liao N, Cui X X, Liao K, et al. Sci China Inf Sci, 2014, 57: 022402-2325 Google Scholar

[16] Muttreja A, Agarwal N, Jha N K. CMOS logic design with independent-gate FinFETs. In: Proceedings of 25th International Conference on Computer Design, Lake Tahoe, 2007. 560--567. Google Scholar

[17] Nanoscale Integration and Modeling (NIMO) Group. Predictive Technology Model. http://ptm.asu.edu/. Google Scholar

[18] Trivedi V P, Fossum J G, Zhang W M. Solid State Electron, 2007, 51: 170-178 CrossRef Google Scholar

[19] Ma K S, Cui X X, Liao K, et al. Sci China Inf Sci, 2015, 58: 022403-178 Google Scholar

[20] Baccarin D, Esseni D, Alioto M. IEEE Trans VLSI Syst, 2012, 20: 1467-1472 CrossRef Google Scholar

[21] Liao K, Cui X X, Liao N, et al. Sci China Inf Sci, 2014, 57: 042408-1472 Google Scholar

[22] Baccarin D, Esseni D, Alioto M. A novel back-biasing low-leakage technique for FinFET forced stacks. In: Proceedings of 2011 IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, 2011. 2079--2082. Google Scholar

[23] Massimo A. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2011, 19: 751-762 CrossRef Google Scholar

[24] Cui X X, Ma K S, Liao K, et al. A Dynamic-adjusting threshold-voltage scheme for FinFETs low power designs. In: Proceedings of IEEE Int Symp on Circuits and Systems, Beijing, 2013. 129--132. Google Scholar

Copyright 2019 Science China Press Co., Ltd. 《中国科学》杂志社有限责任公司 版权所有