logo

SCIENCE CHINA Information Sciences, Volume 59, Issue 10: 102401(2016) https://doi.org/10.1007/s11432-015-5437-0

A snake addressing scheme for phase change memory testing

More info
  • ReceivedJul 17, 2015
  • AcceptedAug 10, 2015
  • PublishedFeb 1, 2016

Abstract

Phase change memory (PCM) is one of the most promising candidates for next generation nonvolatile memory. However, PCM suffers from a variety of faults due to its special device structure and operation mechanism. A snake addressing scheme is introduced into the test algorithms of PCM to reduce the test time and excite proximity disturb faults more effectively. The March test algorithm with the proposed snake addressing scheme is less complex than most traditional test algorithms. In addition to conventional faults, it is capable of covering disturb and parasitic faults. Moreover, when incorporated with the sneak path testing method, it is able to test the read fault, read recovery fault, incomplete program fault 0, and false write fault.


Acknowledgment

This work was supported by National Basic Research Program of China (973) (Grant Nos. 2015CB057201, 2013CBA01903) and R&D project of the Shenzhen Government, China (Grant Nos. JCYJ20140417144423194, JCYJ20140417144423198).


References

[1] Pirovano A, Lacaita A L, Benvenuti A. Electronic Switching in Phase-Change Memories. IEEE Trans Electron Devices, 2004, 51: 452-459 CrossRef ADS Google Scholar

[2] Kang S, Cho W Y, Cho B H. A 0.1-<tex>$\mu{\hbox {m}}$ 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation. IEEE J Solid-State Circuits, 2007, 42: 210-218 CrossRef Google Scholar

[3] Prall K, Ramaswanmy N, Kinney W, et al. An update on emerging memory: progress to 2Xnm. In: Proceedings of IEEE International Memory Workshop, Milan, 2012. 1--5. Google Scholar

[4] Mohammad M G. Fault model and test procedure for phase change memory. IET Comput Digit Tech, 2011, 5: 263-270 CrossRef Google Scholar

[5] Pan X J, Cui X L, Zha J, et al. Modeling and test for parasitic resistance and capacitance defects in PCM. In: Proceedings of 12th Annual Non-Volatile Memory Technology Symposium (NVMTS), Singapore, 2012. 73--76. Google Scholar

[6] Zhang X, Wei Y, Lin X, et al. Critical parasitic capacitance in nano-scale phase-change memory cell. In: Proceedings of IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Chengdu, 2014. 18--20. Google Scholar

[7] Ielmini D, Lacaita A L, Mantegazza D. Recovery and Drift Dynamics of Resistance and Threshold Voltages in Phase-Change Memories. IEEE Trans Electron Devices, 2007, 54: 308-315 CrossRef ADS Google Scholar

[8] Osada K, Kawahara T, Takemura R, et al. Phase change RAM operated with 1.5V CMOS as low cost embedded memory. In: Proceedings of IEEE International Conference on Custom Integrated Circuits, San Jose, 2005. 431--434. Google Scholar

[9] Pirovano A, Redaelli A, Pellizzer F. Reliability Study of Phase-Change Nonvolatile Memories. IEEE Trans Device Mater Relib, 2004, 4: 422-427 CrossRef Google Scholar

[10] Maimon J D, Hunt K K, Burcin L. Chalcogenide memory arrays: characterization and radiation effects. IEEE Trans Nucl Sci, 2003, 50: 1878-1884 CrossRef ADS Google Scholar

[11] Mohammad M G, Terkawi L, Albasman M. Phase change memory faults. In: Proceedings of 19th International Conference on VLSI Design. Held jointly with 5th International Conference on Embedded Systems and Design, Hyderabad, 2006. 6--6. Google Scholar

[12] Wong H S P, Raoux S, Kim S B. Phase Change Memory. Proc IEEE, 2010, 98: 2201-2227 CrossRef Google Scholar

[13] Lacaita A L. Phase change memories: State-of-the-art, challenges and perspectives. Solid-State Electrons, 2006, 50: 24-31 CrossRef ADS Google Scholar

[14] Zhang Z, Xiao W, Park N, et al. Memory module-level testing and error behaviors for phase change memory. In: Proceedings of IEEE 30th International Conference on Computer Design (ICCD), Montreal, 2012. 358--363. Google Scholar

[15] Kannan S, Rajendran J, Karri R. Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories. IEEE Trans Nanotechnology, 2013, 12: 413-426 CrossRef Google Scholar

[16] Wei Y, Lin X, Jia Y, et al. A SPICE model for phase-change memory (PCM) cell based on analytical conductivity model. J Semiconduct, 2012, 33: 1--5. Google Scholar

[17] van de Goor A J, Al-Ars Z. Functional memory faults: a formal notation and a taxonomy. In: Proceedings of IEEE 18th International VLSI Test Symposium (VTS), Montreal, 2000. 281--289. Google Scholar

Copyright 2019 Science China Press Co., Ltd. 《中国科学》杂志社有限责任公司 版权所有

京ICP备18024590号-1