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SCIENCE CHINA Information Sciences, Volume 59, Issue 4: 042411(2016) https://doi.org/10.1007/s11432-015-5471-y

Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology

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  • ReceivedJul 1, 2015
  • AcceptedSep 21, 2015
  • PublishedFeb 1, 2016

Abstract

Single event upset (SEU) is one of the most important origins of soft errors in aerospace applications. As technology scales down persistently, charge sharing is playing a more and more significant effect on SEU of flip-flop. Charge sharing can often bring about multi-node charge collection in storage nodes and non-storage nodes in a flip-flop. In this paper, multi-node charge collection in flip-flop data input and flip-flop clock signal is investigated by 3D TCAD mixed-mode simulations, and the simulate results indicate that single event double transient (SEDT) in flip-flop data input and flip-flop clock signal can also cause a SEU in flip-flop. This novel mechanism is called the SEDT-induced SEU, and it is also verified by heavy-ion experiment in 65 nm twin-well process. The simulation results also indicate that this mechanism is closely related with the well-structure, and the triple-well structure is more effective to increase the SEU threshold of this mechanism than twin-well structure.


Funded by

National Natural Science Foundation of China(61434007)

National Natural Science Foundation of China(61376109)

Project of NUDT(0100066314001)


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