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SCIENCE CHINA Information Sciences, Volume 59, Issue 6: 061406(2016) https://doi.org/10.1007/s11432-016-5560-6

Design for manufacturability and reliability \\in extreme-scaling VLSI

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  • ReceivedDec 14, 2015
  • AcceptedJan 18, 2016
  • PublishedMay 6, 2016

Abstract

In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore's law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.


Acknowledgment

Acknowledgments

This work was supported in part by US National Science Foundation, Semiconductor Research Corporation, National Natural Science Foundation of China, TOSHIBA, and CUHK Direct Grant for Research. The authors would like to thank Meng LI and Wei YE at University of Texas for helpful comments.


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