SCIENCE CHINA Information Sciences, Volume 61, Issue 6: 062401(2018) https://doi.org/10.1007/s11432-016-9106-x

## Impact of self-heating effects on nanoscale Ge p-channel FinFETs with Si substrate

• AcceptedMay 4, 2017
• PublishedNov 20, 2017
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### Abstract

In this paper, self-heating effects (SHE) in nanoscale Ge p-channel FinFETs with Si substrate are evaluated by TCAD simulation. Hydrodynamic transport with modified mobilities and Fourier' s law of heat conduction with modified thermal conductivities are used in the simulation. Ge p-channel single-fin FinFET devices with different S/D extension lengths and fin heights, and multi-fin FinFETs with different fin numbers and fin pitches are successively investigated. Boundary thermal resistances at source, drain and gate contacts are set to 2000 ${\rm~\mu~m^{2}K/W}$ and the substrate thermal boundary condition is set to 300 K so that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below: (i) 14 nm Ge p-channel single-fin FinFETs with a 47 nm fin pitch experience 9.7% on-state current degradation. (ii) Considering the same input power, FinFETs with a longer S/D extension length show a higher lattice temperature and a larger on-state current degradation. (iii) Considering the same input power, FinFETs with a taller fin height show a higher lattice temperature. (iv) The temperature in multi-fin FinFET devices will first increase then saturate with the increasing fin number. At last, thermal resistances in Ge p-channel single-fin FinFETs and multi-fin FinFETs are investigated.

### Acknowledgment

This work was supported by National Natural Science Foundation of China (Grant Nos. 61404005, 61674008, 61421005) and National High Technology Research and Development Program of China (863) (Grant No. 2015AA016501).

• Figure 1

(Color online) Schematic structure of the 14 nm Ge p-channel FinFET. The structure parameters are listed in Table 1.

• Figure 2

(Color online) Cross-sectional views at Planes 1 and 2. The definitions of the structure parameters are presented.

• Figure 3

(Color online) $I_d-V_g$ characteristics of the simulated 14 nm Ge p-channel FinFET. On-state current density is 1581 ${\rm~\mu~A/\mu~m}$. Off-state leakage current density is lower than 100 ${\rm~nA/\mu~m}$. Subthreshold Slope is 76.2 mV/dec and DIBL is 4.5 mV/V.

• Figure 4

(Color online) Spatial temperature distributions of the Ge p-channel single-fin 14 nm FinFET in Plane 1 at different gate voltages. Here $V_d$ is $-$0.63 V. (a) $V_g=-0.35$ V; (b) $V_g=-0.5$ V; (c) $V_g=-0.63$ V.

• Figure 5

(Color online) $I_d-V_d$ characteristics of a 14 nm single-fin FinFET comparing the situations with and without self-heating effects.

• Figure 6

(Color online) Hole temperature distributions (a)–(c) and lattice temperature distributions (d)–(f) in the Ge FinFETs with three different $L_{\rm~sdext}$s 10, 20, 40 nm from left to the right, where the input powers are all 60 ${\rm~\mu~W}$.

• Figure 7

(Color online) Comparison of the different on-state current degradation rates with different $L_{\rm~sdext}$s.

• Figure 8

(Color online) Relationships between the peak, average temperatures and the fin number. Different fin pitches are compared.

• Figure 9

(Color online) Comparison between different on-state current degradations of multi-fin FinFETs with different fin pitches.

• Figure 10

(Color online) Variation tendency of the thermal resistances in multi-fin FinFETs with different fin numbers. Different fin pitches are compared.

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