logo

SCIENCE CHINA Information Sciences, Volume 61, Issue 6: 062401(2018) https://doi.org/10.1007/s11432-016-9106-x

Impact of self-heating effects on nanoscale Ge p-channel FinFETs with Si substrate

More info
  • ReceivedDec 13, 2016
  • AcceptedMay 4, 2017
  • PublishedNov 20, 2017

Abstract

In this paper, self-heating effects (SHE) in nanoscale Ge p-channel FinFETs with Si substrate are evaluated by TCAD simulation. Hydrodynamic transport with modified mobilities and Fourier' s law of heat conduction with modified thermal conductivities are used in the simulation. Ge p-channel single-fin FinFET devices with different S/D extension lengths and fin heights, and multi-fin FinFETs with different fin numbers and fin pitches are successively investigated. Boundary thermal resistances at source, drain and gate contacts are set to 2000 ${\rm~\mu~m^{2}K/W}$ and the substrate thermal boundary condition is set to 300 K so that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below: (i) 14 nm Ge p-channel single-fin FinFETs with a 47 nm fin pitch experience 9.7% on-state current degradation. (ii) Considering the same input power, FinFETs with a longer S/D extension length show a higher lattice temperature and a larger on-state current degradation. (iii) Considering the same input power, FinFETs with a taller fin height show a higher lattice temperature. (iv) The temperature in multi-fin FinFET devices will first increase then saturate with the increasing fin number. At last, thermal resistances in Ge p-channel single-fin FinFETs and multi-fin FinFETs are investigated.


Acknowledgment

This work was supported by National Natural Science Foundation of China (Grant Nos. 61404005, 61674008, 61421005) and National High Technology Research and Development Program of China (863) (Grant No. 2015AA016501).


References

[1] Yeo Y-C, Gong X, van Dal Mark J H, et al. Germanium-based transistors for future high performace and low power logic applications. In: Proceedings of IEEE International Electron Device Meeting, Washington, 2015. 28--31. Google Scholar

[2] Kim R, Avci U E, Young I A. CMOS performance benchmarking of Si, InAs, GaAs, and Ge nanowire n- and pMOSFETs with Lg=13 nm based on atomistic quantum transport simulation including strain effects. In: Proceedings of IEEE International Electron Device Meeting, Washington, 2015. 875--878. Google Scholar

[3] Wu H, Luo H, Zhou H, et al. First experimental demonstration of Ge 3D FinFET CMOS circuits. In: Proceedings of Symposium on VLSI Technology, Kyoto, 2015. 58--59. Google Scholar

[4] Kang E S, Anwar S, Ahmadi M T, et al. The impact of germanium in strained Si/relaxed Si1-xGex on carrier performance in nondegenerate and degenerate regimes. J Semicond, 2013. 34: 062001. Google Scholar

[5] Waldron N, Sioncke S, Franco J, et al. Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200$\mu$S/$\mu$m at 50 nm Lg using a replacement Fin RMG flow. In: Proceedings of IEEE International Electron Device Meeting, Washington, 2015. 799--802. Google Scholar

[6] Zhou J H, Chang H D, Zhang X F, et al. Fabrication of a novel RF switch device with high performance using In0.4Ga0.6As MOSFET technology. J Semicond, 2016. 37: 024005. Google Scholar

[7] Sasaki Y, Ritzenthaler R, Keersgieter A D, et al. A comparison of arsenic and phosphorus extension by room temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7 nm) technology relevant fin dimensions. In: Proceedings of Symposium on VLSI Technology, Kyoto, 2015. 30--31. Google Scholar

[8] Veloso A, Hellings G, Cho M J, et al. Gate-all-around NWFETs vs. Triple-gate FinFETs: junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-Vt CMOS. In: Proceedings of Symposium on VLSI Technology, Kyoto, 2015. 138--139. Google Scholar

[9] Mertens H, Ritzenthaler R, Hikavyy A, et al. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates. In: Proceedings of Symposium on VLSI Technology, Honolulu, 2016. 158--159. Google Scholar

[10] Yakimets D, Eneman G, Schuddinck P. Vertical GAAFETs for the Ultimate CMOS Scaling. IEEE Trans Electron Devices, 2015, 62: 1433-1439 CrossRef ADS Google Scholar

[11] Deleonibus S. Looking into the future of Nanoelectronics in the Diversification Efficient Era. Sci China Inf Sci, 2016, 59: 061401 CrossRef Google Scholar

[12] Cheng K, Khakifirooz A. Fully depleted SOI (FDSOI) technology. Sci China Inf Sci, 2016, 59: 061402 CrossRef Google Scholar

[13] Stellari F, Jenkins K A, Weger A J, et al. Self-heating measurement of 14-nm FinFET SOI transistors using 2-D time-resolved emission. IEEE Trans Electron Dev, 2016, 63: 2016--2022. Google Scholar

[14] Wahab M A, Shin S H, Alam M A. 3D Modeling of Spatio-temporal Heat-transport in III-V Gate-all-around Transistors Allows Accurate Estimation and Optimization of Nanowire Temperature. IEEE Trans Electron Devices, 2015, 62: 3595-3604 CrossRef ADS Google Scholar

[15] Jang D, Bury E, Ritzenthaler E, et al. Self-heating on bulk FinFET from 14nm down to 7 nm node. In: Proceedings of IEEE International Electron Device Meeting, Washington, 2015. 289--292. Google Scholar

[16] Jiang H, Xu N, Chen B, et al. Experimental investigation of self-heating effect (SHE) in multiple-fin SOI FinFETs. Semicond Sci Tech, 2014. 29: 115021. Google Scholar

[17] Ma L, Feng S, Zhang Y. Evaluation of the drainsource voltage effect on AlGaAs/InGaAs PHEMTs thermal resistance by the structure function method. J Semicond, 2014, 35: 094006 CrossRef ADS Google Scholar

[18] Gong X Q, Feng S W, Yue Y, et al. Thermal analysis in high power GaAs-based laser diodes. J Semicond, 2016. 37: 044011. Google Scholar

[19] Dames C, Chen G. Theoretical phonon thermal conductivity of Si/Ge superlattice nanowires. J Appl Phys, 2004. 95: 682--693. Google Scholar

[20] Bury E, Kaczer B, Mitard J, et al. Characterization of self-heating in high-mobility Ge FinFET pMOS devices. In: Proceedings of Symposium on VLSI Technology, Kyoto, 2015. 60--61. Google Scholar

[21] Synopsys. Sentaurus device user guide, v D-2010.03, 2010. Google Scholar

[22] Arora N D, Hauser J R, Roulston D J. Electron and hole mobilities in silicon as a function of concentration and temperature. IEEE Trans Electron Dev, 1982, ED-29: 292--295. Google Scholar

[23] Darwish M N, Lentz J L, Pinto M R. An improved electron and hole mobility model for general purpose device simulation. IEEE Trans Electron Devices, 1997, 44: 1529-1538 CrossRef ADS Google Scholar

[24] Canali C, Majni G, Minder R. Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature. IEEE Trans Electron Devices, 1975, 22: 1045-1047 CrossRef ADS Google Scholar

[25] Hellings G, Eneman G, Krom R. Electrical TCAD Simulations of a Germanium pMOSFET Technology. IEEE Trans Electron Devices, 2010, 57: 2539-2546 CrossRef ADS Google Scholar

[26] Wang L P, Brown A R, Nedjalkov M, et al. Impact of self-heating on the statistical variability in bulk and SOI FinFETs. IEEE Trans Electron Dev, 2015, 62: 2016--2112. Google Scholar

[27] Marco G P, Alessandro C. Quantum simulation of self-heating effects in rough Si nanowire FETs. In: Proceedings of IEEE International Workshop on Computational Electronics, Paris, 2014. 65--67. Google Scholar

[28] Fiegna C, Yang Y, Sangiorgi E. Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation. IEEE Trans Electron Devices, 2008, 55: 233-244 CrossRef ADS Google Scholar

[29] Ting-Yen Chiang , Banerjee K, Saraswat K C. Analytical thermal model for multilevel VLSI interconnects incorporating via effect. IEEE Electron Device Lett, 2002, 23: 31-33 CrossRef ADS Google Scholar

[30] Sadi T, Thobel J L, Dessenne F. Microscopic simulation of electron transport and self-heating effects in InAs nanowire MISFETs. In: Proceedings of IEEE International Conference on Simulation of Semiconductor Processes and Devices, Bologna, 2010. 107--110. Google Scholar

[31] Shrivastava M, Agrawal M, Mahajan S. Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures. IEEE Trans Electron Devices, 2012, 59: 1353-1363 CrossRef ADS Google Scholar

  • Figure 1

    (Color online) Schematic structure of the 14 nm Ge p-channel FinFET. The structure parameters are listed in Table 1.

  • Figure 2

    (Color online) Cross-sectional views at Planes 1 and 2. The definitions of the structure parameters are presented.

  • Figure 5

    (Color online) Spatial temperature distributions of the Ge p-channel single-fin 14 nm FinFET in Plane 1 at different gate voltages. Here $V_d$ is $-$0.63 V. (a) $V_g=-0.35$ V; (b) $V_g=-0.5$ V; (c) $V_g=-0.63$ V.

  • Figure 8

    (Color online) Hole temperature distributions (a)–(c) and lattice temperature distributions (d)–(f) in the Ge FinFETs with three different $L_{\rm~sdext}$s 10, 20, 40 nm from left to the right, where the input powers are all 60 ${\rm~\mu~W}$.

  • Figure 15

    (Color online) Variation tendency of the thermal resistances in multi-fin FinFETs with different fin numbers. Different fin pitches are compared.

  • Table 1   Structure parameters of the simulated FinFET
    Structure parameter Value
    Raised S/D height, $H_{\rm~sd}$ 52 nm
    Stop layer height, $H_{\rm~stop}$ 40 nm
    Substrate layer height, $H_{\rm~sub}$ 40 nm
    Fin height, $H_{\rm~fin}$ 42 nm
    Raised S/D length,$L_{\rm~sd}$ 20 nm
    S/D extension length, $L_{\rm~sdext}$ 20 nm
    Gate length, $L_{g}$ 20 nm
    Pitch, $W_{\rm~pitch}$ 47 nm
    Fin width, $W_{\rm~fin}$ 7 nm
    Channel doping, $n$ type 1$\times{\rm~10^{15}cm^{-3}}$
    Stop layer doping, $n$ type 1$\times{\rm~10^{18}cm^{-3}}$
    Source/drain doping, $p$ type 2$\times{\rm~10^{19}cm^{-3}}$
    Gate oxide thickness (EOT) 0.68 nm
  • Table 2   Mobility model parameters $^{\rm~a)}$
    Parameter Unit Hole Parameter Unit Hole
    Arora ModelExtended Canali Model
    $A_{\rm~min}$ ${\rm~cm^2/Vs}$ 1900 $\nu_{\rm~sat}$ cm/s 1.4$\times10^7$
    $\alpha_m$ 1 $-$2.3 $\beta_{\rm~exp}$ ${\rm~cm^{5/3}V^{-2/3}s^{-1}}$ 0.17
    Enhanced Lombardi Model
    B cm/s 1.993$\times10^5$ A 1 1.5
    C ${\rm~cm^{5/3}V^{-2/3}s^{-1}}$ 4875 $\alpha_\bot$ ${\rm~cm^3}$ 0
    $N_0$ ${\rm~cm^{-3}}$ 1 $N_l$ ${\rm~cm^{-3}}$ 1
    $N_2$ ${\rm~cm^{-3}}$ 1 $\nu$ 1 1
    $\lambda$ 1 0.0317 $\eta$ ${\rm~V^{2}cm^{-1}s^{-1}}$ $2.0546\times~10^{30}$
    k 1 1 $a_{\rm~other}$ 1 0
    $\delta$ ${\rm~cm^2/Vs}$ $1.705\times~10^{11}$ $l_{\rm~crit}$ cm $1\times~10^{-7}$

    a) Other mobility parameters not listed here are default values in Sentaurus [21].

Copyright 2019 Science China Press Co., Ltd. 《中国科学》杂志社有限责任公司 版权所有

京ICP备18024590号-1