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SCIENCE CHINA Information Sciences, Volume 61, Issue 6: 062404(2018) https://doi.org/10.1007/s11432-017-9305-x

All-metal electrodes vertical gate-all-around device with self-catalyzed selective grown InAs NWs array

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  • ReceivedSep 29, 2017
  • AcceptedNov 23, 2017
  • PublishedApr 19, 2018

Abstract

With the scaling down of field-effect transistors (FETs) to improve their performance, 3D vertical surrounding gate structure has drawn great attention. On the other hand, concerning the channel materials, InAs nanowires (NWs) have been demonstrated to have great potential in FET due to their high mobility and other excellent electrical properties. Here, we report the first all-metal electrodes vertical gate-all-around (VGAA) FET fabricated using self-catalyzed selective grown InAs NWs array grown by metal organic chemical vapor deposition. A typical transistor we fabricated has an on-state current larger than 37 $\mu$A/$\mu$m when the drain voltage and gate voltage are +0.6 V and +3.0 V, respectively, and an on-off ratio overłinebreak 3 orders of magnitudes. We have measured 34 transistors in total, and most of them have the on-off ratio between rm $~10^2$and rm $~10^4$ Annealing is observed to improve the contact property, increase the on-state current, but decrease the on-off ratio. The ways to improve the performance of InAs NW VGAA FET are discussed.


Acknowledgment

This work was supported by National Basic Research Program of China (Grant No. 2012CB932700(02, 01)), National Key Research and Development Plan (Grant No. 2016YFA0200802), and National Natural Science Foundation of China (Grant No. 61621061). We thank Dr. Tuanwei SHI and Dr. Mengqi FU for the valuable discussions, Mr. Jun XU and Dr. Xing LI for assistance in FIB.


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  • Figure 1

    (a) SEM image of one InAs NWs array (tilted at 30$^\circ$); (b) a high magnification SEM image of InAs NWs (tilted at 30$^\circ$); (c) a high-resolution TEM image of one typical InAs NW, the arrow points the growing direction.

  • Figure 2

    Schematic diagrams showing the fabrication process of VGAA FETs. (a) The self-catalyzed NWs array; (b) the sample after depositing the bottom metal (Ti/Al/W) and defining the bottom electrode; (c) the sample after defining the height of the bottom electrode with S1813; (d) the sample after removing the metal on the NWs using RIE and wet etching; (e) the sample after fabricating the spacer layer between the bottom and gate electrodes; (f) the sample after depositing $\rm~HfO_2$ layer using ALD; (g) the sample after depositing and definiting the gate electrode; (h) the sample after fabricating the spacer layer between the gate and top electrodes; (i) the sample after removing the $\rm~HfO_2$ on the top part of InAs NWs; (j) the sample after defining vias and removing the gate oxide in the vias; (k) the sample after depositing the top metal layer; (l) the sample after separating the three electrodes and finishing the fabrication of the VGAA FETs.

  • Figure 3

    (a) SEM image of the sample after fabricating the bottom electrodes; (b) SEM image of the sample after depositing the gate metal; (c) SEM image of one VGAA FET; (d) SEM image of VGAA FETs array; (e) the schematic diagrams of the cross sectional structure of a VGAA device (top diagram) and the equivalent circuit of the center part of a device (bottom diagram); (f) the cross sectional SEM of a VGAA device marked by fake colors. Only one NW in the device is shown to be clear. The left two images are the enlarged images of the areas outlined in the main image.

  • Figure 4

    (Color online) (a) The output curves and (b) the transfer curve of a typical VGAA FET.

  • Figure 5

    (Color online) Comparison of the electrical performance of the same VGAA FET before and after annealing.protect łinebreak (a) The output curves before annealing; (b) the output curves after annealing; (c) the transfer curve before annealing. The inset is the same curve in logarithmic coordinate; (d) the transfer curve after annealing.

  • Figure 6

    (Color online) (a) The output curves of a typical planar MOSFET based on single InAs NW with large diameter, and the insert is the SEM image of the same device; (b) the transfer curve of the same device in (a).

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