SCIENCE CHINA Information Sciences, Volume 61, Issue 6: 060422(2018) https://doi.org/10.1007/s11432-017-9424-y

Neuromorphic computing with memristive devices

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  • ReceivedDec 7, 2017
  • AcceptedFeb 26, 2018
  • PublishedMay 15, 2018


Technology advances in the last a few decades have resulted in profound changes in our society, from workplaces to living rooms to how we socialize with each other. These changes in turn drive further technology developments, as the exponential growth of data demands ever increasing computing power. However, improvements in computing capacity from device scaling alone is no longer sufficient, and new materials, devices, and architectures likely need to be developed collaboratively to meet present and future computing needs. Specifically, devices that offer co-located memory and computing characteristics, as represented by memristor devices and memristor-based computing systems, have attracted broad interest in the last decade. Besides tremendous appeal in data storage applications, memristors offer the potential for efficient hardware realization of neuromorphic computing architectures that can effectively address the memory and energy walls faced by conventional von Neumann computing architectures. In this review, we evaluate the state-of-the-art in memristor devices and systems, and highlight the potential and challenges of applying such devices and architectures in neuromorphic computing applications. New directions that can lead to general, efficient in-memory computing systems will also be discussed.


This work was supported in part by National Science Foundation (NSF) (Grant Nos. ECCS-1708700, CCF-1617315). We would like to thank F CAI, J LEE and J SHIN for helpful discussions.


[1] Yang J J, Strukov D B, Stewart D R. Memristive devices for computing. Nat Nanotech, 2013, 8: 13-24 CrossRef PubMed ADS Google Scholar

[2] Kim K H, Gaba S, Wheeler D. A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications. Nano Lett, 2012, 12: 389-395 CrossRef PubMed ADS Google Scholar

[3] Pershin Y V, Di Ventra M. Neuromorphic, digital, and quantum computation with memory circuit elements. Proc IEEE, 2012, 100: 2071-2080 CrossRef Google Scholar

[4] Gaba S, Knag P, Zhang Z Y, et al. Memristive devices for stochastic computing. In: Proceedings of IEEE International Symposium on Circuits and Systems, Melbourne, 2014. 2592--2595. Google Scholar

[5] Zidan M, Jeong Y J, Shin J H. Field-programmable crossbar array (FPCA) for reconfigurable computing. IEEE Trans Multi-Scale Comput Syst, 2017, CrossRef Google Scholar

[6] Borghetti J, Snider G S, Kuekes P J. `Memristive' switches enable `stateful' logic operations via material implication. Nature, 2010, 464: 873-876 CrossRef PubMed ADS Google Scholar

[7] Mead C. Neuromorphic electronic systems. Proc IEEE, 1990, 78: 1629-1636 CrossRef Google Scholar

[8] Indiveri G, Horiuchi T K. Frontiers in neuromorphic engineering. Front Neurosci, 2011, 5: 118 CrossRef Google Scholar

[9] Chicca E, Stefanini F, Bartolozzi C. Neuromorphic electronic circuits for building autonomous cognitive systems. Proc IEEE, 2014, 102: 1367-1388 CrossRef Google Scholar

[10] Gaba S, Sheridan P, Zhou J. Stochastic memristive devices for computing and neuromorphic applications. Nanoscale, 2013, 5: 5872-5878 CrossRef PubMed ADS arXiv Google Scholar

[11] Prezioso M, Merrikh-Bayat F, Hoskins B D. Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature, 2015, 521: 61-64 CrossRef PubMed ADS arXiv Google Scholar

[12] Indiveri G, Linares-Barranco B, Legenstein R. Integration of nanoscale memristor synapses in neuromorphic computing architectures. Nanotechnology, 2013, 24: 384010 CrossRef PubMed ADS arXiv Google Scholar

[13] Zidan M A, Chen A, Indiveri G. Memristive computing devices and applications. J Electroceram, 2017, 39: 4-20 CrossRef Google Scholar

[14] Chua L O, Sung Mo Kang L O. Memristive devices and systems. Proc IEEE, 1976, 64: 209-223 CrossRef Google Scholar

[15] Strukov D B, Snider G S, Stewart D R. The missing memristor found. Nature, 2008, 453: 80-83 CrossRef PubMed ADS Google Scholar

[16] Govoreanu B, Kar G S, Chen Y Y, et al. 10$\times$10 nm$^2$ Hf/HfO$_x$ crossbar resistive RAM with excellent performance, reliability and low-energy operation. In: Proceedings of IEEE International Electron Devices Meeting, Washington, 2011. Google Scholar

[17] Torrezan A C, Strachan J P, Medeiros-Ribeiro G. Sub-nanosecond switching of a tantalum oxide memristor. Nanotechnology, 2011, 22: 485203 CrossRef PubMed ADS Google Scholar

[18] Lee M J, Lee C B, Lee D. A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta$_{2}$O$_{5-x}$/TaO$_{2-x}$ bilayer structures. Nat Mater, 2011, 10: 625-630 CrossRef PubMed ADS Google Scholar

[19] Valov I, Lu W D. Nanoscale electrochemistry using dielectric thin films as solid electrolytes. Nanoscale, 2016, 8: 13828-13837 CrossRef PubMed ADS Google Scholar

[20] Younis A, Chu D, Lin X. High-performance nanocomposite based memristor with controlled quantum dots as charge traps. ACS Appl Mater Interfaces, 2013, 5: 2249-2254 CrossRef PubMed Google Scholar

[21] Stoliar P, Rozenberg M, Janod E. Nonthermal and purely electronic resistive switching in a Mott memory. Phys Rev B, 2014, 90: 45146 CrossRef ADS Google Scholar

[22] Wong H S P, Raoux S, Kim S B. Phase change memory. Proc IEEE, 2010, 98: 2201-2227 CrossRef Google Scholar

[23] Diao Z, Li Z, Wang S. Spin-transfer torque switching in magnetic tunnel junctions and spin-transfer torque random access memory. J Phys-Condens Matter, 2007, 19: 165209 CrossRef ADS Google Scholar

[24] Sheridan P M, Cai F, Du C. Sparse coding with memristor networks. Nat Nanotech, 2017, 12: 784-789 CrossRef PubMed Google Scholar

[25] Chang T, Jo S H, Kim K H. Synaptic behaviors and modeling of a metal oxide memristive device. Appl Phys A, 2011, 102: 857-863 CrossRef ADS Google Scholar

[26] Hasegawa T, Ohno T, Terabe K. Learning abilities achieved by a single solid-state atomic switch. Adv Mater, 2010, 22: 1831-1834 CrossRef PubMed Google Scholar

[27] Jo S H, Chang T, Ebong I. Nanoscale Memristor Device as Synapse in Neuromorphic Systems. Nano Lett, 2010, 10: 1297-1301 CrossRef PubMed ADS Google Scholar

[28] Kim S, Choi S H, Lu W. Comprehensive physical model of dynamic resistive switching in an oxide memristor. ACS Nano, 2014, 8: 2369-2376 CrossRef PubMed Google Scholar

[29] Seo K, Kim I, Jung S. Analog memory and spike-timing-dependent plasticity characteristics of a nanoscale titanium oxide bilayer resistive switching device. Nanotechnology, 2011, 22: 254023 CrossRef PubMed ADS Google Scholar

[30] Kim S, Du C, Sheridan P. Experimental demonstration of a second-order memristor and its ability to biorealistically implement synaptic plasticity. Nano Lett, 2015, 15: 2203-2211 CrossRef PubMed ADS Google Scholar

[31] Du C, Ma W, Chang T. Biorealistic implementation of synaptic functions with oxide memristors through internal ionic dynamics. Adv Funct Mater, 2015, 25: 4290-4299 CrossRef Google Scholar

[32] Kuzum D, Yu S, Philip Wong H S. Synaptic electronics: materials, devices and applications. Nanotechnology, 2013, 24: 382001 CrossRef PubMed ADS Google Scholar

[33] Wang Z, Joshi S, Savel'ev S E. Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing. Nat Mater, 2017, 16: 101-108 CrossRef PubMed ADS Google Scholar

[34] Zidan M A, Jeong Y J, Lu W D. Temporal learning using second-order memristors. IEEE Trans Nanotechnol, 2017, 16: 721-723 CrossRef ADS Google Scholar

[35] Ma W, Chen L, Du C. Temporal information encoding in dynamic memristive devices. Appl Phys Lett, 2015, 107: 193101 CrossRef ADS Google Scholar

[36] Zhu X, Du C, Jeong Y J. Emulation of synaptic metaplasticity in memristors. Nanoscale, 2017, 9: 45-51 CrossRef PubMed Google Scholar

[37] Yang Y, Chen B, Lu W D. Memristive physically evolving networks enabling the emulation of heterosynaptic plasticity. Adv Mater, 2015, 27: 7720-7727 CrossRef PubMed Google Scholar

[38] Merolla P A, Arthur J V, Alvarez-Icaza R. A million spiking-neuron integrated circuit with a scalable communication network and interface. Science, 2014, 345: 668-673 CrossRef PubMed ADS Google Scholar

[39] Benjamin B V, Gao P, McQuinn E. Neurogrid: a mixed-analog-digital multichip system for large-scale neural simulations. Proc IEEE, 2014, 102: 699-716 CrossRef Google Scholar

[40] Furber S B, Galluppi F, Temple S. The SpiNNaker project. Proc IEEE, 2014, 102: 652-665 CrossRef Google Scholar

[41] Schemmel J, Briiderle D, Griibl A, et al. A wafer-scale neuromorphic hardware system for large-scale neural modeling. In: Proceedings of IEEE International Symposium on Circuits and Systems, Paris, 2010. 1947--1950. Google Scholar

[42] Pfeil T, Grübl A, Jeltsch S. Six networks on a universal neuromorphic computing substrate. Front Neurosci, 2013, 7: 11 CrossRef Google Scholar

[43] Indiveri G, Liu S C. Memory and information processing in neuromorphic systems. Proc IEEE, 2015, 103: 1379-1397 CrossRef Google Scholar

[44] Alibart F, Zamanidoost E, Strukov D B. Pattern classification by memristive crossbar circuits using ex situ and in situ training. Nat Commun, 2013, 4: 2072 CrossRef PubMed ADS Google Scholar

[45] Sheridan P M, Du C, Lu W D. Feature extraction using memristor networks. IEEE Trans Neural Netw Learning Syst, 2016, 27: 2327-2336 CrossRef PubMed Google Scholar

[46] Choi S, Sheridan P, Lu W D. Data clustering using memristor networks. Sci Rep, 2015, 5: 10492 CrossRef PubMed ADS Google Scholar

[47] Sheridan P, Ma W, Lu W. Pattern recognition with memristor networks. In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, 2014. 1078--1081. Google Scholar

[48] Adhikari S P, Yang C J, Kim H. Memristor bridge synapse-based neural network and its learning. IEEE Trans Neural Netw Learning Syst, 2012, 23: 1426-1435 CrossRef PubMed Google Scholar

[49] Hu M, Strachan J P, Grafals E M, et al. Dot-product engine for neuromorphic computing. In: Proceedings of the 53rd Annual Design Automation Conference, Austin, 2016. Google Scholar

[50] Choi S, Shin J H, Lee J. Experimental demonstration of feature extraction and dimensionality reduction using memristor networks. Nano Lett, 2017, 17: 3113-3118 CrossRef PubMed ADS Google Scholar

[51] Yu S, Chen P Y, Cao Y, et al. Scaling-up resistive synaptic arrays for neuro-inspired architecture: challenges and prospect. In: Proceedings of International Electron Devices Meeting, Washington, 2015. Google Scholar

[52] Sheridan P, Lu W D. Defect consideratons for robust sparse coding using memristor arrays. In: Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, Boston, 2015, 137--138. Google Scholar

[53] Ma W, Cai F, Du C, et al. Device nonideality effects on image reconstruction using memristor arrays. In: Proceedings of 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2016. Google Scholar

[54] Kumar S, Strachan J P, Williams R S. Chaotic dynamics in nanoscale NbO$_{2}$ Mott memristors for analogue computing. Nature, 2017, 548: 318-321 CrossRef PubMed ADS Google Scholar

[55] Tuma T, Pantazi A, Le Gallo M. Stochastic phase-change neurons. Nat Nanotech, 2016, 11: 693-699 CrossRef PubMed ADS Google Scholar

[56] Chen B, Cai F X, Zhou J T, et al. Efficient in-memory computing architecture based on crossbar arrays. In: Proceedings of International Electron Devices Meeting, Washington, 2015. Google Scholar

  • Figure 1

    (Color online) Categories of memristive devices based on the RS mechanism [13]@ Copyright 2017 Springer Nature.

  • Figure 2

    (Color online) Bipolar switching behavior of an RRAM device. (Inset) Crosspoint structure that is typically used to implement the two-terminal RRAM devices and arrays [13]@ Copyright 2017 Springer Nature.

  • Figure 3

    (Color online) Analog RS in a Ag/$\alpha$-Si based memristive device, showing measured (blue) and calculated (orange) I-V characteristics of the device [25]@ Copyright 2010 American Chemical Society.

  • Figure 4

    (Color online) Schematic of a memristor-based network structure. A memristor is formed at each cross-point and can simultaneously store data and process information, in ways similar to a biological synapse [25]protect łinebreak @ Copyright 2010 American Chemical Society.

  • Figure 5

    (Color online) (a) Mimicking the biological synapse using a single memristor device; (b) measured STDP behavior from a memristor [25]@ Copyright 2010 American Chemical Society.

  • Figure 6

    (Color online) (a) Schematic of a memristor crossbar-based computing system. The input neurons (green) and the leaky integrating output neurons (pink) are connected to the rows and columns of the crossbar, respectively. An output neuron collects currents flown from all memristor devices in the column associated with the neuron. The memristor devices can be programmed to different conductance states (represented in greyscale), through internal ion redistribution (inset). (b) Scanning electron micrograph (SEM) image of a fabricated memristor array and the memristor chip (lower left) [24]protect łinebreak @ Copyright 2017 Springer Nature.

  • Figure 7

    (Color online) Natural image processing using the memristor crossbar network. (a) The original 120$\times$120 image to be processed is divided into non-overlapping 4$\times$4 patches; (b) an example of a 4$\times$4 patch from the original image; (c) the experimentally reconstructed patch from the 16$\times$32 memristor crossbar; (d) membrane potentials of the neurons during sparse coding The red horizontal line marks the threshold parameter. Neurons having membrane potential above the threshold are active, while the other neurons will have exactly zero activity; (e) reconstructed image [24]@ Copyright 2017 Springer Nature.

  • Figure 8

    (Color online) Block diagram showing the different layers that can be reconfigured in a possible reconfigurable in-memory computing architecture [5]@ Copyright 2017 IEEE.

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