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SCIENCE CHINA Information Sciences, Volume 61, Issue 6: 060422(2018) https://doi.org/10.1007/s11432-017-9424-y

Neuromorphic computing with memristive devices

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  • ReceivedDec 7, 2017
  • AcceptedFeb 26, 2018
  • PublishedMay 15, 2018

Abstract

Technology advances in the last a few decades have resulted in profound changes in our society, from workplaces to living rooms to how we socialize with each other. These changes in turn drive further technology developments, as the exponential growth of data demands ever increasing computing power. However, improvements in computing capacity from device scaling alone is no longer sufficient, and new materials, devices, and architectures likely need to be developed collaboratively to meet present and future computing needs. Specifically, devices that offer co-located memory and computing characteristics, as represented by memristor devices and memristor-based computing systems, have attracted broad interest in the last decade. Besides tremendous appeal in data storage applications, memristors offer the potential for efficient hardware realization of neuromorphic computing architectures that can effectively address the memory and energy walls faced by conventional von Neumann computing architectures. In this review, we evaluate the state-of-the-art in memristor devices and systems, and highlight the potential and challenges of applying such devices and architectures in neuromorphic computing applications. New directions that can lead to general, efficient in-memory computing systems will also be discussed.


Acknowledgment

This work was supported in part by National Science Foundation (NSF) (Grant Nos. ECCS-1708700, CCF-1617315). We would like to thank F CAI, J LEE and J SHIN for helpful discussions.


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  • Figure 1

    (Color online) Categories of memristive devices based on the RS mechanism [13]@ Copyright 2017 Springer Nature.

  • Figure 2

    (Color online) Bipolar switching behavior of an RRAM device. (Inset) Crosspoint structure that is typically used to implement the two-terminal RRAM devices and arrays [13]@ Copyright 2017 Springer Nature.

  • Figure 3

    (Color online) Analog RS in a Ag/$\alpha$-Si based memristive device, showing measured (blue) and calculated (orange) I-V characteristics of the device [25]@ Copyright 2010 American Chemical Society.

  • Figure 4

    (Color online) Schematic of a memristor-based network structure. A memristor is formed at each cross-point and can simultaneously store data and process information, in ways similar to a biological synapse [25]protect łinebreak @ Copyright 2010 American Chemical Society.

  • Figure 5

    (Color online) (a) Mimicking the biological synapse using a single memristor device; (b) measured STDP behavior from a memristor [25]@ Copyright 2010 American Chemical Society.

  • Figure 6

    (Color online) (a) Schematic of a memristor crossbar-based computing system. The input neurons (green) and the leaky integrating output neurons (pink) are connected to the rows and columns of the crossbar, respectively. An output neuron collects currents flown from all memristor devices in the column associated with the neuron. The memristor devices can be programmed to different conductance states (represented in greyscale), through internal ion redistribution (inset). (b) Scanning electron micrograph (SEM) image of a fabricated memristor array and the memristor chip (lower left) [24]protect łinebreak @ Copyright 2017 Springer Nature.

  • Figure 7

    (Color online) Natural image processing using the memristor crossbar network. (a) The original 120$\times$120 image to be processed is divided into non-overlapping 4$\times$4 patches; (b) an example of a 4$\times$4 patch from the original image; (c) the experimentally reconstructed patch from the 16$\times$32 memristor crossbar; (d) membrane potentials of the neurons during sparse coding The red horizontal line marks the threshold parameter. Neurons having membrane potential above the threshold are active, while the other neurons will have exactly zero activity; (e) reconstructed image [24]@ Copyright 2017 Springer Nature.

  • Figure 8

    (Color online) Block diagram showing the different layers that can be reconfigured in a possible reconfigurable in-memory computing architecture [5]@ Copyright 2017 IEEE.

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