SCIENCE CHINA Information Sciences, Volume 62, Issue 2: 022401(2019) https://doi.org/10.1007/s11432-018-9555-8

Efficient evaluation model including interconnect resistance effect for large scale RRAM crossbar array matrix computing

More info
  • ReceivedMar 24, 2018
  • AcceptedAug 23, 2018
  • PublishedDec 28, 2018


Crossbar architecture has been considered as an efficient means to execute a matrix-vector multiplication computation. An efficient evaluation model for this computation including the interconnect resistance effect on the high density resistive random access memmory (RRAM) crossbar array is proposed in this paper. The proposed model considers the interconnect resistance impacts on the columns and rows separately. The simulation results indicate that the computing speed of the proposed model can be boosted by over three orders of magnitude with the computation deviation of 7.7% in comparison with the precise comprehensive model in the 64 kb crossbar array fabricated at the 14 nm technology node. Based on the proposed evaluation model, the impacts of the parameters including nonlinearity and load resistance, on the computation are discussed along with solutions to improve the computational performance.


This work was supported by National Natural Science Foundation of China (Grant Nos. 61334007, 61421005), and Shenzhen Science and Technology Innovation Committee (Grant No. JCYJ2017041215- 0411676).


[1] Wong H S P, Lee H Y, Yu S. Metal-Oxide RRAM. Proc IEEE, 2012, 100: 1951-1970 CrossRef Google Scholar

[2] Hudec B, Hsu C W, Wang I T. 3D resistive RAM cell design for high-density storage class memory-a review. Sci China Inf Sci, 2016, 59: 061403 CrossRef Google Scholar

[3] Waser R, Dittmann R, Staikov G. Redox-Based Resistive Switching Memories - Nanoionic Mechanisms, Prospects, and Challenges. Adv Mater, 2009, 21: 2632-2663 CrossRef Google Scholar

[4] Borghetti J, Snider G S, Kuekes P J. `Memristive' switches enable `stateful' logic operations via material implication. Nature, 2010, 464: 873-876 CrossRef PubMed ADS Google Scholar

[5] Yang J J, Strukov D B, Stewart D R. Memristive devices for computing. Nat Nanotech, 2013, 8: 13-24 CrossRef PubMed ADS Google Scholar

[6] Huang P, Kang J, Zhao Y. Reconfigurable Nonvolatile Logic Operations in Resistance Switching Crossbar Array for Large-Scale Circuits.. Adv Mater, 2016, 28: 9758-9764 CrossRef PubMed Google Scholar

[7] Hu M, Li H, Chen Y. Memristor crossbar-based neuromorphic computing system: a case study.. IEEE Trans Neural Netw Learning Syst, 2014, 25: 1864-1878 CrossRef PubMed Google Scholar

[8] Upadhyay N K, Joshi S, Yang J J. Synaptic electronics and neuromorphic computing. Sci China Inf Sci, 2016, 59: 061404 CrossRef Google Scholar

[9] Cao J, Li R. Fixed-time synchronization of delayed memristor-based recurrent neural networks. Sci China Inf Sci, 2017, 60: 032201 CrossRef Google Scholar

[10] Yu S, Gao B, Fang Z. A low energy oxide-based electronic synaptic device for neuromorphic visual systems with tolerance to device variation.. Adv Mater, 2013, 25: 1774-1779 CrossRef PubMed Google Scholar

[11] Hu M, Li H, Wu Q, et al. Hardware realization of BSB recall function using memristor crossbar arrays. In: Proceedings of the 49th Annual Design Automation Conference, San Francisco, 2012. 498--503. Google Scholar

[12] Gu P, Li B X, Tang T Q, et al. Technological exploration of RRAM crossbar array for matrix-vector multiplication. In: Proceedings of the 19th Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, 2015. 106--111. Google Scholar

[13] Gao L, Chen P Y, Yu S. Demonstration of Convolution Kernel Operation on Resistive Cross-Point Array. IEEE Electron Device Lett, 2016, 37: 870-873 CrossRef ADS Google Scholar

[14] Li H, Gao B, Chen Z. A learnable parallel processing architecture towards unity of memory and computing. Sci Rep, 2015, 5: 013330 CrossRef PubMed ADS Google Scholar

[15] Semiconductor Industry Association. International Technology Roadmap for Semiconductors. 2015. https://www.semiconductors.org/main/2015_international_technology_roadmap_for_semiconductors_itrs/. Google Scholar

[16] Chen A. A Comprehensive Crossbar Array Model With Solutions for Line Resistance and Nonlinear Device Characteristics. IEEE Trans Electron Devices, 2013, 60: 1318-1326 CrossRef ADS Google Scholar

[17] Vontobel P O, Robinett W, Kuekes P J. Writing to and reading from a nano-scale crossbar memory based on memristors. Nanotechnology, 2009, 20: 425204 CrossRef PubMed ADS Google Scholar

[18] Deng Y, Huang P, Chen B. RRAM Crossbar Array With Cell Selection Device: A Device and Circuit Interaction Study. IEEE Trans Electron Devices, 2013, 60: 719-726 CrossRef ADS Google Scholar

[19] Huang P, Liu X Y, Chen B. A Physics-Based Compact Model of Metal-Oxide-Based RRAM DC and AC Operations. IEEE Trans Electron Devices, 2013, 60: 4090-4097 CrossRef ADS Google Scholar

[20] Sheridan P M, Cai F, Du C. Sparse coding with memristor networks.. Nat Nanotech, 2017, 12: 784-789 CrossRef PubMed Google Scholar

[21] Li C, Hu M, Li Y. Analogue signal and image processing with large memristor crossbars. Nat Electron, 2018, 1: 52-59 CrossRef Google Scholar

  • Figure 1

    (Color online) Computation deviation of the connection matrix method vs. array size ($n~\times~n$) at different tech nodes.

  • Figure 4

    (a) Equivalent circuit diagram of row (word line) $k$; (b) simplified circuit diagram of row $k$.

  • Figure 5

    (Color online) Voltage distribution at word lines with (a) uniform and (b) random cell resistance distribution.

  • Figure 6

    (Color online) Voltage and computation deviation rate at the nearest/farthest output with the (a) uniform and (b) random cell resistance distribution of the three methods vs. the crossbar array size at the 14 nm tech node.

  • Figure 7

    (Color online) Computation time of three methods with different crossbar array sizes ($n~\times~n$).

  • Figure 10

    (Color online) Voltage at the farthest output vs. HRS ratio with different nonlinearities. The array size is set to 64 $\times$ 64.

  • Table 1   Simulation parameters used for model validation
    Parameter Value
    Interconnect resistance ($R_{\rm~wire}$) 10.88 $\Omega$
    Low resistance state ($R_{\rm~on}$) 10 k$\Omega$
    Load resistance ($R_s$) 5 k$\Omega$
    Input voltage amplitude 1 V
    Resistance ratio ($R_{\rm~on}/R_{\rm~off}$) 1000

Copyright 2020 Science China Press Co., Ltd. 《中国科学》杂志社有限责任公司 版权所有