1. Changsha, China Changsha China 410073
2. 湖南长沙 changsha China 410073
When multiplication and addition can be implemented by physical processes in memristor crossbar arrays in parallel, hardware implementation of memristor spiking neural networks (SNNs) has obvious advantages in power and area efficiency compared to software implementation of SNNs. This paper proposes an area efficient memristor SNN for hardware implementation. The spikes in the memristor SNNs are simplified as step signals and the number of synapses between a preneuron and a postneuron is limited to one. This paper also presents a supervised learning method that approximates the step function as a modified sigmoid function to train the memristor SNNs. The XOR problem, the Fisher Iris dataset and the MNIST dataset are employed to validate the proposed memristor SNNs and learning method. Simulation results indicate that synapses used in the memristor SNNs are several times (6.7 times for the XOR problem and 2.2 times for the Fisher Iris dataset) less than existing literatures that are similar to SpikeProp to carry out the same problems. The proposed learning method can train the memristor SNNs successfully while previous learning algorithms cannot converge with less than four sub-connections (synapses between a preneuron and a postneuron). What’s more, this paper obtains a classification accuracy of 100% for the Fisher Iris dataset, and a classification accuracy of 97.61% for the MNIST dataset.
This work was supported by the National Natural Science Foundation of China (Grant No. 61332003) and HPCL(Grant No. 201501-02).
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