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SCIENCE CHINA Information Sciences, Volume 62, Issue 6: 062408(2019) https://doi.org/10.1007/s11432-018-9863-6

Circuit design of RRAM-based neuromorphic hardware systems for classification and modified Hebbian learning

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  • ReceivedSep 26, 2018
  • AcceptedMar 28, 2019
  • PublishedMay 7, 2019

Abstract

This paper proposes a solution to the learning of neuromorphic hardware systems based on metal-oxideresistive random access memory (RRAM) arrays, which are used as binary electronic synapses. A modified Hebbian learning method is developed to update the binary synaptic weights, and mixed-signal circuits are designed to implement the proposed learning method. The circuits are verified by SPICE, and systematic simulations are also conducted to verify the capability of the neuromorphic system to process relatively large databases. The results show that the system presents high processing speed ($10^6$ examples per second) for both classification and learning, and a high recognition accuracy (up to 95.6%) on the MNIST database.


Acknowledgment

This work was supported by National Natural Science Foundation of China (Grant Nos. 61421005, 61334007, 61604005).


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  • Figure 1

    (Color online) An overview of the neuromorphic system in this work. The outputs of Layer 1 are directly conveyed to Layer 2 as inputs. A postsynaptic neuron in Layer 1 and the corresponding presynaptic neuron in Layer 2 form a hidden neuron together. Note that Layer 2 uses delayed clocks.

  • Figure 2

    Communications among modules in each layer.

  • Figure 3

    (Color online) An analogy between biological synapses and RRAM synapses. (a) A biological synapse;protect łinebreak (b) RRAM synapses. In our modified Hebbian learning method, there are two types of synapses: excitatory synapses and inhibitory synapses.

  • Figure 4

    (Color online) (a) Measured transient response of an RRAM device during a SET process. The device switches from HRS to LRS. (b) Measured transient response of an RRAM device during a RESET process. The device switches from LRS to HRS. (c) Measured and simulated resistance distribution of the fabricated RRAM devices. The devices have two stable resistance states and show reliable LTD and LTP behaviors under successive RESET and SET pulses. The measured results indicate that the RRAM devices can be used as qualified binary synapses.

  • Figure 5

    (Color online) Schematic diagram of the 1/3 bias scheme used in this work. The RRAM cell in the middle is selected, while others are not. By applying operation voltages ($V_X$ and 0 on the selected columns and rows, $\frac13V_X$ and $\frac23V_X$ on other columns and rows) on each column and each row simultaneously, the selected RRAM cell can be switched to either HRS or LRS.

  • Figure 6

    (Color online) Flowchart for the neuromorphic system based on the modified Hebbian learning.

  • Figure 7

    (Color online) An example of the transitions of RRAM cells during the modified Hebbian learning. (a) Example input; (b) LTD; (c) LTP.

  • Figure 8

    (Color online) Analog parts of the proposed neuron circuits. (a) The analog part (either an E-part or an I-part) of a presynaptic neuron. $V_{\rm~PRE}$ is the output of the analog part of the presynaptic neuron and connects to a column of the RRAM array. (b) The analog part of a postsynaptic neuron. Synapses is an I/O port that links to a row of the RRAM array.

  • Figure 9

    (Color online) The SPICE transient simulations of analog parts of the proposed neuron circuits. The overlapped pulses from both sides can change the state of the RRAM synapse. At about $t=500$ ns, RRAM_1 changes to HRS, while RRAM_2 changes to HRS first, and then back to LRS. Then the two cells keep their resistance states unchanged during the subsequent operations. (a) Waveforms of signal CLK_1M, VPRE_1, VPRE_2 and VPOST; (b) waveforms of signal VRRAM_1, IRRAM_1, VRRAM_2 and IRRAM_2.

  • Figure 10

    (Color online) (a) Circuit design of a threshold controller; (b) the SPICE transient simulations of the threshold controller. A clock signal is applied to the threshold controller, and a dynamic threshold that rises gradually and declines rapidly is generated.

  • Figure 11

    Digital parts of the proposed neuron circuits and the neuron manager module. (a) The digital part of a presynaptic neuron. The digital part of a presynaptic neuron is implemented by only a positive-edge-triggered D flip-flop. (b) The digital parts of a postsynaptic neuron. These digital circuits accept the output signal from the comparator in the analog part of the neuron, and accept a serial of control signals, and finally output the firing state of the neuron. (c) Neuron manager. The neuron manager generates control signals to the digital parts of postsynaptic neurons, and implements the WTA rule by sending a Sign signal that implies whether a winner neuron occurs.

  • Figure 12

    (Color online) The SPICE transient simulations of digital parts of the proposed neuron circuits during unsupervised learning. No label is needed in unsupervised learning, and the postsynaptic neurons compete with each other until one of them becomes the winner and fires. (a) Waveforms of signal CLK_1M_D1, CMP1, CMP2, and CMP3; (b) waveforms of signal Fire1, Fire2, Fire3, and Sign.

  • Figure 13

    (Color online) The SPICE transient simulations of digital parts of the proposed neuron circuits during supervised learning. Alongside with each example, a label should be input to force one of the postsynaptic neurons to fire.protect łinebreak (a) Waveforms of CLK_1M_D1, Label1, Label2, Label3, and Sign; (b) waveforms of CMP1, CMP2, CMP3, Fire1, Fire2, and Fire3.

  • Figure 14

    (Color online) (a) Circuit design of an NRP controller. (b) The SPICE transient simulations of the NRP controller. The NRP selection and the firing of a neuron itself control whether the neuron is allowed to fire during the subsequent operations together.

  • Figure 15

    (Color online) (a) Circuit design of a learning controller. (b) The SPICE transient simulations of the learning controller. The learning controller generates two signals that are crucial for learning. The pulse of Learning immediately follows the pulse of direction, and the time difference is fixed to 100 ns.

  • Figure 16

    Resistance matrices of part of the RRAM arrays before and after learning. Before learning, the initial states of RRAM synapses are arbitrary; after learning, information is stored into the RRAM synapses, which also indicates the memory of the example is created in the system. Excitatory synapses and inhibitory synapses show opposite evolutions.

  • Figure 17

    (Color online) (a) Recognition accuracy as a function of the number of hidden neurons. When inhibitory synapses are used, the system achieves a better recognition accuracy (up to 95.6%). (b) Recognition accuracy as a function of device variations. Although the recognition accuracy of the system decreases as the device variations increase, the system shows a relatively good tolerance. When 10 thousand neurons are used, the system can maintain a high recognition accuracy ($>$ 90%) when the device variation is up to 20%.

  • Figure 18

    (Color online) The impact of line resistance on the recognition accuracy. RL is the line resistance between two adjacent RRAM cells, and RLRS is the average resistance of LRS RRAM cells. Systems with more hidden neurons are more sensitive to the IR drop issue.

  • Table 1   Synaptic current levels
    Presynaptic neuron Fire Rest
    Excitatory synapse LRS 1 0
    HRS 0 0
    Inhibitory synapse LRS 0 1
    HRS 0 0
  • Table 2   Resource utilization of digital circuits of the system with differenct number of hidden neurons
    Hidden neurons Logic utilization (in ALMs) Total registers
    10 88 913
    100 441 1273
    1000 4188 4861

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