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SCIENCE CHINA Information Sciences, Volume 62, Issue 12: 220401(2019) https://doi.org/10.1007/s11432-019-2651-x

Recent progress in devices and circuits based on wafer-scale transitionmetal dichalcogenides

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  • ReceivedJul 25, 2019
  • AcceptedSep 18, 2019
  • PublishedNov 12, 2019

Abstract

Two-dimensional layered materials (2DLMs) have triggered a broad researchthrust over the last decade worldwide. Different from the gapless graphene,transition metal dichalcogenides (TMDs) exhibit versatile bandstructure, withbandgap sizes ranging from semi-metallic to over 2 eV. Therefore, 2D-TMDscan be utilized in various applications from logic to optoelectronicdevices. In this review we first introduce the latest developments of thewafer-scale synthesis of continuous TMD films, then we present recentadvances in large scale devices and circuits based on TMD films, includinglogic, memory, optoelectronic and analog devices. We also provide aperspective and a look at the future device applications based onwafer-scale 2D-TMDs.


Acknowledgment

This work was supported by National Key Research and Development Program (Grant No. 2016-YFA0203900), Shanghai Municipal Science and Technology Commission (Grant No. 18JC1410300), and National Natural Science Foundation of China (Grant No. 61874154).


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  • Figure 1

    (Color online) (a) Schematic illustration of an experimental setup and photos of 2-inch MoS$_{2}$/sapphire and bare sapphire substrate [48]@Copyright 2017 American Chemical Society. (b) The optical image of grown MoS$_{2}$ film with PTAS seeding promoter and without seeding promoter. Insets from left to right: optical image of film with PTAS, atomic force microscope (AFM) image of film with PTAS, AFM image of film without PTAS, corresponding height cross-section analysis [54]@Copyright 2014 American Chemical Society. (c) Substrate with not fully covered triangular MoS$_{2}$ film, substrate with continuous monolayer MoS$_{2}$, continuous MoS$_{2}$ film with multilayer starting to grow and continuous MoS$_{2}$ film with high-density multilayer islands [55]@Copyright 2016 John Wiley and Sons. (d) Optical image, structure model, AFM image of monolayer WS$_{2}$ grown on graphite and height profile along the black line in AFM image [56]@Copyright 2015 American Chemical Society. (e) Schematic diagram of a face-to-face metal-precursor supply route towards synthesizing MoS$_{2}$ on glass [36] @Copyright 2018 Springer Nature.

  • Figure 2

    (Color online) (a) A typical setup of wafer-scale MoS$_{2}$ growth by sulfurizing of a pre-deposited Mo metal thin film [59] @Copyright 2014 John Wiley and Sons. (b) Schematic illustration of the synthetic procedure for the ALD-based WS$_{2}$ film [34]@Copyright 2013 American Chemical Society. (c) Temperature profile of thermal decomposition process for the synthesis of MoS$_{2}$ layers and AFM image of the as-grown MoS$_{2}$ on SiO$_{2}$/Si substrate [55]@Copyright 2016 John Wiley and Sons. (d) Diagram of MOCVD growth setup, precursors were introduced to the growth setup with individual mass flow controllers [32]@Copyright 2015 Springer Nature.

  • Figure 3

    (Color online) (a) Left: the fabricated ML-MoS$_{2}$ FET and logic gate array on the wafer. Right: voltage transfer curve and gain of the inverter [27]@Copyright 2018 John Wiley and Sons. (b) Left: optical image of the ReS$_{2}$ transistors and logic gates, such as NOR, NAND, and NOT gates. Right: voltage transfer characteristics and signal gain of the NOT gate at $V_{\rm~DD}$ = 1 V [90]@Copyright 2017 American Chemical Society. (c) Schematic depiction of a chemically synthesized MoTe$_{2}$ inverter. The left inset is the circuit diagram for the inverter [61]@Copyright 2019 Springer Nature. (d) Left: schematic illustration of a complementary inverter based on Si nanomembrane (NM) and MoS$_{2}$ FETs. Right: voltage transfer curves of the inverter at different $V_{\rm~DD}$ [97]@Copyright 2016 John Wiley and Sons. (e) Left: illustration of the monolayer MoS$_{2}$ and WSe$_{2}$ FET built on the sapphire substrate. Right: the voltage gain plotted of input voltage. The maximum gain exceeds 110 with a low input voltage [89]@Copyright 2016 American Chemical Society. (f) Left: schematic illustration along with corresponding optical microscopy image of the CMOS inverter built up on WSe$_{2}$ and MoSe$_{2}$ grown by MGSG. Right: output voltage and gain of the integrated inverter as a function of the input voltage [98]@Copyright 2019 John Wiley and Sons.

  • Figure 4

    (Color online) (a) Illustration diagram of the MoS$_{2}$ FET fabricated by gate-first process. (b) Layout (left) and the optical photograph (right) of fabricated test chip using the design flow. (c) Statistics of $V_{\rm~T}$ of MoS$_{2}$ FETs from gate-last and gate-first fabrication technologies. (d) Schematic, micrograph, and waveform results of the fabricated representative XNOR gate (left) and latch circuit (right) [8]@Copyright 2016 American Chemical Society.

  • Figure 5

    (Color online) (a) Schematic diagram of an inverter (top) and an individual MoS$_{2}$ transistor (bottom) in gate-first technology. (b) Output voltage of the MoS$_{2}$ logic inverter as a function of the input voltage. (c) Microscope image of the microprocessor containing 115 MoS$_{2}$ transistors and measured 0.6 mm$^{2}$ in size. (d) Operation timing diagram of the microprocessor [9]@Copyright 2017 Springer Nature. (e) Optical images of an inverter, NAND, NOR, AND and XOR gates on solution-processable MoS$_{2}$ nanosheets. (f) The measured voltage transfer curve and signal gain of the integrated MoS$_{2}$ inverter. Logic operation of the (g) NAND, (h) NOR, and (i) XOR gates with a power supply of $V_{\rm~DD}$ = 5 V.protect łinebreak (j) Experimental truth table for the logic half-adder. The logic half-adder is implemented by using an AND gate and an XOR gate [104] @Copyright 2018 Springer Nature.

  • Figure 6

    (Color online) (a) The 3D schematic illustration structure of 2T/2R TMD-TCAM cells, using two MoS$_{2}$ FET fabricate two RRAM. (b) The 3D schematic of the 1T/1R structure, which is the component of the 2T/2R TCAM cell. (c) Circuit diagram of the 2T/2R TCAM cell based on two RRAM define match or mismatch states with the stored data bit `1' or `0'. (d) Circuit diagram of the 1T/1R structure. (e) Set and reset measurements of the 1T/1R DRAM for 45 cycles. (f) Distribution of the set and reset voltages [106] @Copyright 2019 Springer Nature. (g) $I$-$V$ characteristics and the schematic illustration of the MoS$_{2}$-PVP based flexible memory device [107] @Copyright 2012 John Wiley and Sons. (h) $I$-$V$ characteristics and the schematic illustration of the MoS$_{2}$-ZIF-8 based flexible memory device [108] @Copyright 2014 American Chemical Society. (i) $I$-$V$ characteristics and the schematic illustration of the MoS$_{2}$-GO based memory device [109] @Copyright 2012 John Wiley and Sons.

  • Figure 7

    (Color online) (a) Optical image of visible-light photodetector arrays based on homogeneous MoS$_{2}$ film on a 4 inch SiO$_{2}$/Si wafer. (b) Time-resolved photocurrents of the device measured at $P$ = 12.5 mW$\times~$cm$^{~-~2~}$ under different bias voltages [55] @Copyright 2016 John Wiley and Sons. (c) Microscope photograph of MoS$_{2}$/WS$_{2}$ vertical heterojunction device arrays on the SiO$_{2}$/Si substrate. (d) Schematic diagram of the MoS$_{2}$/WS$_{2}$ vertical heterojunction phototransistor.protect łinebreak (e) Current-voltage characteristics of the MoS$_{2}$/WS$_{2}$ vertical heterojunction phototransistor measured in dark. The inset in (e) shows the band alignment for a WS$_{2}$ and MoS$_{2}$ vertical heterojunction [115]@Copyright 2016 American Chemical Society. (f) Schematic illustration of the photodetector based on doped MoS$_{2}$. The inset in (f): transfer curves of photodetectors based on Nb-doped MoS$_{2}$ measured with the exposure of the photodetectors to 282 nW light powers at a 550 nmprotect łinebreak wavelength laser. (g) Photographic image of a homogeneous large-area film of Nb-doped MoS$_{2}$ which was transferred onto a 2 inch SiO$_{2}$/Si wafer. (h) Work function distribution across a 5.3 mm $\times~$ 4.0 mm area divided into 100 regions [116]@Copyright 2019 American Chemical Society.

  • Figure 8

    (Color online) (a) Optical image of the CVD MoS$_{2}$ in the ground-signal-ground structure (GSG). (b) Short circuit current gain $|h_{21}|$ versus frequency. (c) Maximum frequency of oscillation $f_{\rm~max}$ versus frequency [119]@Copyright 2015 American Chemical Society. (d) Electrical characteristics of flexible MoS$_{2}$ FETs ($L_g$ = 500 nm) at 300 K. Inset is an optical photograph of CVD MoS$_{2}$ FETs on the flexible substrate. (e) Input and output voltage waveforms of CS amplifier with a gain of 15 dB. The CS amplifier is based on MoS$_{2}$ flexible TFT ($f_{\rm~RF}\approx~1.4$ MHz). (f) Output frequency spectrum of MoS$_{2}$ FET-based RF mixer ($f_{\rm~RF}\approx~1.4$ MHz, $f_{\rm~LO}\approx~1.1$ MHz, $f_{\rm~IF}\approx~300$ kHz). The inset shows the conversion gain of the mixer is ca. $-$17 dB. (g) MoS$_{2}$ FET-based wireless AM (amplitude modulation) receiver output spectrum. The distance between transmit and receiver antenna is 5 m, and the carrier frequency ($\omega_{\rm~C}$) is 1.5 MHz [120]@Copyright 2015 John Wiley and Sons. (h) Schematic illustration of bilayer MoS$_{2}$ RF transistor. (i) The SEM images of MoS$_{2}$ RF transistor with dual-channel structure scale bar is 500 nm. (j) Small-signal current gain $|h_{21}|$ versus frequency for device with gate length of 90 nm. (k) Unilateral power gain $U$ versus frequency for device with gate length of 90 nm [121]@Copyright 2018 Springer Nature.

  • Table 1   Summary of recent large-scale continuous TMDs synthetic methods
    Syntheticpar methods Materials Key preparation conditions Doping typepar & mobility (cm$^{2}$/Vs)par & ON/OFF ratio Domain size ($\mu$m) par & coverage Ref.
    MoS$_{2}$ Independent carrier gas channels n-type par 40 par $\sim$10$^{6}$ $\sim$2par 100% [48]
    MoS$_{2}$ Aromatic molecules as seeding promotes n-type par – par – $\sim~$60par 60% [54]
    One-step direct MoS$_{2}$ Low pressure to introduce multilayer dots n-type par 70 par 10$^{8}$ 10–20 par 100% [55]
    deposition WSe$_{2}$ Introduction of H$_{2}$ in reaction furnace p-type par 90 par 10$^{5}$ 10–50 par – [56]
    WS$_{2}$ Substrate: cleaved graphite surface exceptionally high-temperature at 1100$^{\circ}$C Non-doped par –par – 15 par – [36]
    MoS$_{2}$ Face-to-face metal source supply substrate: soda-lime glass n-type par 6.3–11.4 par 10$^{5}$–10$^{6}$ 200par 43%–100% [59]
    MoS$_{2}$ Mo metal evaporated by E-beam n-type par 4.1–8.7 par – –par 100%
    Two-step vapor WS$_{2}$ WoO$_{3}$ deposited by ALD p-type par 3.9 par – 0.01–0.02par 100%
    chalcogenization MoS$_{2}$ (NH$_{4})_{2}$MoS$_{4}$ decomposed into MoS$_{2}$ at 450$^{\circ}$C n-typepar 14 par 5$\times$10$^{2}$ –par – [34]
    MOCVD MoS$_{2}$ MOCVD precisely control the concentration of precursors n-type par 30 par 10$^{6}$ 1par 100% [55]
    MBE MoTe$_{2}$ Modulating the source supply with mass flow p-type par 32 par 10$^{7}$ –par 100% [32]
  • Table 2   Summary of TMDs-based inverters
    Channel material Mobility (cm$^{2}$/Vs) Gate dielectric Substrate Inverter type $V_{\rm~DD}$ par (V) Inverter gain Ref.
    MoS$_{2}$ 4.3 35 nm Al$_{2}$O$_{3}$ Polyimide NMOS 15 16 [99]
    MoS$_{2}$ 33.73 30 nm HfO$_{2}$ Sapphire NMOS 3 23 [27]
    ReS$_{2}$ 0.9 Ion gel SiO$_{2}$/Si NMOS 1 3.5 [90]
    Graphene & MoS$_{2}$ 17 20 nm Al$_{2}$O$_{3}$ SiO$_{2}$/Si NMOS 3 12 [79]
    MoTe$_{2}$ 130 12 nm HfO$_{2}$ SiO$_{2}$/Si PMOS $-$6 35 [61]
    MoS$_{2}$ 3 22 nm Al$_{2}$O$_{3}$ SiO$_{2}$/Si NMOS 5 50 [9]
    MoS$_{2}$ 7–11 30 nm Al$_{2}$O$_{3}$ SiO$_{2}$/Si NMOS 5 20 [104]
    n-MoS$_{2~}$ & par p-Si-NW 1.3 & 14 50 nm Al$_{2}$O$_{3}$ SiO$_{2}$/Si CMOS 5 16 [97]
    n-MoS$_{2}$ & p-WSe$_{2}$ 30 & 55 Ion gel Sapphire CMOS 2 110 [89]
    n-WSe$_{2}$ & p-MoSe$_{2}$ 11.49 & 10.68 Ionic liquid Sapphire CMOS 3 23 [98]
    n-MoS$_{2~}$ & p-MoS$_{2}$ 10 HfO$_{2}$ SiO$_{2}$/Si CMOS 3 22 [12]
    n-PtSe$_{2~}$ & p-PtSe$_{2}$ 14 & 15 30 nm HfO$_{2}$ Sapphire CMOS 3 1 [28]

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