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SCIENCE CHINA Information Sciences, Volume 63, Issue 10: 209402(2020) https://doi.org/10.1007/s11432-019-2658-x

Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors

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  • ReceivedApr 7, 2019
  • AcceptedSep 19, 2019
  • PublishedMay 20, 2020

Abstract

There is no abstract available for this article.


Acknowledgment

This work was supported in part by National Key Research and Development Plan (Grant No. 2016YFA0200504), National Science and Technology Major Project (Grant No. 2017ZX02315001-004), Program of National Natural Science Foundation of China (Grant Nos. 61421005, 61774012, 61574010), Beijing Innovation Center for Future Chips Foundation (Grant No. KYJJ2016008), and the 111 Project (Grant No. B18001).


References

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  • Figure 1

    (Color online) (a) The cross section view of GAA SNWTs with non ideal structure ($l_1~\neq~l_2$); (b) comparison of the $I_{\rm~D}$-$V_{\rm~G}$ characteristics of GAA SNWTs with symmetrical and asymmetrical gate structure; (c) the unfolded drawing of the asymmetrical gate cut $l_2$ to form two cosine shaped gate edges; (d) the effective gate length changes with $l_2$ when $l_1$ is constant; (e) comparison of $I_{\rm~D}$-$V_{\rm~G}$ characteristics between the asymmetrical GAA SNWT and the equivalently symmetrical device; (f) the relative change of $L_{\rm~eff}$ to $l_1$ compared to the change of $l_2$.

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