logo

SCIENTIA SINICA Informationis, Volume 46, Issue 6: 800-810(2016) https://doi.org/10.1360/N112014-00217

A systemic performance estimation and moduli set selection method for residue number systems

More info
  • ReceivedSep 7, 2015
  • AcceptedJan 28, 2016
  • PublishedMay 26, 2016

Abstract

The residue number system (RNS) has been receiving considerable attention for many decades owing to its inherent carry-free and parallel properties in addition, subtraction, and multiplication operations. In RNS-based systems, the method by which the moduli set is selected and evaluation of its performance are important issues. A systemic performance evaluation method for RNS based on the properties of the moduli set is proposed in this paper. By abstracting the inherent properties of moduli sets, such as the complexity of arithmetic units, utilization ratio of dynamic range, parallelism, and balance between residue channels, information can be provided on moduli set selection and performance estimation before circuit implementation. Furthermore, we also propose a new multi-channel moduli set that utilizes a new radix component in this paper. Performance analysis and comparison results show that the proposed multi-channel moduli set has good systemic performance.


Funded by

国家自然科学基金(61571083)

中央高校基本业务费(ZYGX2014J009)


References

[1] Chang C H, Molahosseini A S, Zarandi A A E, et al. IEEE Circ Syst Mag, 2015, 15: 26-44 CrossRef Google Scholar

[2] Wang W, Li X, Wang W, et al. IEEE Trans Signal Process, 2015, 63: 3317-3331 CrossRef Google Scholar

[3] Wang W, Swamy M N S, Ahmad M O, et al. A comprehensive study of three moduli sets for residue arithmetic. In: Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering, Edmonton, 1999, 1: 513-518. Google Scholar

[4] Mohan P V A. IEEE Trans Circ Syst II: Express Briefs, 2007, 54: 775-779 CrossRef Google Scholar

[5] Wey C L, Lin S Y. VLSI implementation of residue-to-binary converters for digital signal processing. In: Proceedings of IEEE International Conference on Electro/Information Technology, Chicago, 2007. 536-541. Google Scholar

[6] Cao B, Chang C H, Srikanthan T. IEEE Trans Circuits Syst I: Fundamental Theory Appl, 2003, 50: 1296-1303 CrossRef Google Scholar

[7] Sheu M H, Lin S H, Chen C Y, et al. IEEE Trans Circ Syst II: Express Briefs, 2004, 51: 152-155 CrossRef Google Scholar

[8] Cao B, Srikanthan T, Chang C H. IEEE Proc Comput Digital Tech, 2005, 152: 687-696 CrossRef Google Scholar

[9] Cao B, Chang C H, Srikanthan T. IEEE Trans Circ Syst I: Regular Papers, 2007, 54: 1041-1049 CrossRef Google Scholar

[10] Wang W, Swamy M N S, Ahmad M O, et al. VLSI Design, 2002, 14: 183-191 CrossRef Google Scholar

[11] Wang W, Swamy M N S, Ahmad M O. Moduli selection in RNS for efficient VLSI implementation. In: Proceedings of the International Symposium on Circuits and Systems (ISCAS'03), Bangkok, 2003, 4: 512-515. Google Scholar

[12] Ma S, Hu J H, Wang C H. IEEE Trans Circ Syst I: Regular Papers, 2013, 60: 2962-2972 CrossRef Google Scholar

[13] Piestrak S J. Design of residue generators and multioperand modular adders using carry-save adders. IEEE Trans Comput, 1994, 423: 68-77. Google Scholar

[14] Dugdale M. IEEE Trans Circ Syst II: Analog Digital Signal Process, 1992, 39: 325-329 CrossRef Google Scholar

[15] Patel R A, Benaissa M, Powel N, et al. ELMMA: a new low power high-speed adder for RNS. In: Proceedings of IEEE Workshop on Signal Processing Systems (SIPS 2004), Austin, 2004. 95-100. Google Scholar

[16] Patel R A, Boussakta S. IEEE Trans Comput, 2007, 56: 1484-1492 CrossRef Google Scholar

[17] Dimitrakopoulos G, Vergos H T, Nikolos D, et al. A systematic methodology for designing area-time efficient parallel-prefix modulo adders. In: Proceedings of the International Symposium on Circuits and System (ISCAS'03), Bangkok, 2003, 5: 225-228. Google Scholar

[18] Lin S H, Sheu M H. IEEE Trans Circuits Syst II: Express Briefs, 2008, 55: 897-901 CrossRef Google Scholar

[19] Vergos H T, Efstathiou C. IEEE Trans Circuits Syst II: Express Briefs, 2008, 55: 1041-1045 CrossRef Google Scholar

[20] Efstathiou C, Vergos H T, Nikolos D. IEEE Trans Comput, 2004, 53: 1211-1216 CrossRef Google Scholar

[21] Patel R A, Benaissa M, Boussakta S, et al. Electron Lett, 2005, 41: 231-232 CrossRef Google Scholar

[22] Patel R A, Benaissa M, Boussakta S. IEEE Trans Comput, 2007, 56: 572-576 CrossRef Google Scholar

Copyright 2020 Science China Press Co., Ltd. 《中国科学》杂志社有限责任公司 版权所有

京ICP备18024590号-1