logo

SCIENTIA SINICA Informationis, Volume 47, Issue 2: 260-274(2017) https://doi.org/10.1360/N112016-00081

Prebond through silicon vias test based on time-to-digital conversion}{Prebond through silicon vias test based on time-to-digital conversion

More info
  • ReceivedJun 20, 2016
  • AcceptedAug 16, 2016
  • PublishedDec 14, 2016

Abstract

Defects in through silicon vias (TSV) not only lead to the variation of the propagation delay but also to that of the transition delay, which is more sensitive to TSV faults. A non-invasive approach for pre-bond TSV tests based on time-to-digital conversion is proposed to detect resistive open and leakage faults with picosecond accuracy. The TSVs are used as capacitive loads of their driving gates. The pulse visiting the cyclic shrinkage cells will then shrink until it vanishes completely. The shrinkage amount is digitized and compared with the expected fault-free value. The fault detection experiments are carried out with HSPICE simulations using realistic 45-nm CMOS technology models. The results show the effectiveness in the detection of resistive open defects 0.2 K$\Omega$ above and equivalent leakage resistance less than 40 M$\Omega$. . This scheme is capable of TSV quality binning; the frequencies of the input pulse or test clock have no strict limit. The estimated area overhead of the design for testability is negligible for realistic dies.


Funded by

国家自然科学基金(61274036)

国家自然科学基金(61371025)

国家自然科学基金(61474036)

国家自然科学基金(61540011)

国家自然科学基金(31601224)

安徽省高校省级自然科学研究重点项目(KJ2016A001)

安徽省高校省级自然科学研究重点项目(KJ2016A006)

安徽省高校省级自然科学研究重点项目(KJ2014A005)

安徽省自然科学基金青年项目(1608085QF145)


References

[1] Liu J, Wu X, Liang H G, et al. Optimizing the number of leaf nodes and TSVs in three dimensional scan tree. Sci Sin Inform, 2014, 44: 1203-1215 [刘军, 吴玺, 梁华国, 等. 三维扫描树叶子节点和TSVs数量的优化方法. 中国科学: 信息科学, 2014, 44: 1203-1215]. Google Scholar

[2] Chang H, Liang H G, Li Y, et al. Optimized stacking order for 3D-stacked ICs considering the probability and cost of failed bonding. In: Proceedings of the International Symposium on VLSI Design, Automation and Test, Hsinchu, 2014. 283-286. Google Scholar

[3] Rajski J, Tyszer J. Fault diagnosis of TSV-based interconnects in 3-D stacked designs. In: Proceedings of IEEE International Test Conference, Anaheim, 2013. 1-9. Google Scholar

[4] Jiang L, Ye F M, Xu Q, et al. On effective and efficient in-field TSV repair for stacked 3D ICs. In: Proceedings of the 50th ACM/IEEE Design Automation Conference, Austin, 2013. 1-6. Google Scholar

[5] Huang S-Y, Lin Y-H, Huang L-R, et al. Programmable leakage test and binning for TSVs with self-timed timing control. IEEE Trans Comput Aid D, 2013, 32: 1265-1273 CrossRef Google Scholar

[6] Huang S-Y, Lee J-Y, Tsai K-H, et al. Pulse-vanishing test for interposers wires in 2. 5-D IC. IEEE Trans Comput Aid D, 2014, 33: 1258-1268 CrossRef Google Scholar

[7] Jiang L, Huang X W, Xie H F, et al. A novel TSV probing technique with adhesive test interposer. In: Proceedings of the 33rd IEEE International Conference on Computer Design, New York, 2015. 597-604. Google Scholar

[8] Lueck M R, Gregory C W, Malta D, et al. High density interconnect bonding of heterogeneous materials using non-collapsible microbumps at 10$\upmu$m pitch. In: Proceedings of the IEEE International 3D Systems Integration Conference, San Francisco, 2013. 1-5. Google Scholar

[9] Lu J-H, Loke W-F, Jung B. Millimeter-wave wireless interconnect for 3-D SIC testing. IEEE Des Test, 2014, 31: 29-37 CrossRef Google Scholar

[10] Deutsch S, Chakrabarty K. Contactless pre-bond TSV test and diagnosis using ring oscillators and multiple voltage levels. IEEE Trans Comput Aid D, 2014, 33: 774-785 CrossRef Google Scholar

[11] Huang L-R, Huang S-Y, Sunter S, et al. Oscillation-based prebond TSV test. IEEE Trans Comput Aid D, 2013, 32: 1440-1444 CrossRef Google Scholar

[12] Montanes R R, Arumi D, Figueras J. Post-bond test of through-silicon vias with open defects. In: Proceedings of the 19th IEEE European Test Symposium, Paderborn, 2014. 1-6. Google Scholar

[13] Natale G D, Flottes M L, Rouzeyre B, et al. Built-in self-test for manufacturing TSV defects before bonding. \linebreak In: Proceedings of the IEEE VLSI Test Symposium, Napa, 2014. 1-6. Google Scholar

[14] Chen P-Y, Wu C-W, Kwai D-M. On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding.\linebreak In: Proceedings of the IEEE VLSI Test Symposium, Santa Cruz, 2010. 263-268. Google Scholar

[15] Noia B, Chakrabarty K. Pre-bond probing of TSVs in 3D stacked ICs. In: Proceedings of the IEEE International Test Conference, Anaheim, 2011. 1-10. Google Scholar

[16] Chen P-Y, Wu C-W, Kwai D-M. On-chip TSV testing for 3D IC before bonding using sense amplification. \linebreak In: Proceedings of the Asian Test Symposium, Taichung, 2009. 450-455. Google Scholar

[17] Rabaey J M, Chandrakasan A, Nikolic B. Digital Integrated Circuits-A Design Perspective. 2nd ed. New Jersey: Prentice Hall, 2003. 25-32. Google Scholar

[18] Arumi D, Montanes R R, Figueras J. Pre-bond testing of weak defects in TSVs. In: Proceedings of the IEEE International On-Line Testing Symposium, Catalunya, 2014. 31-36. Google Scholar

[19] Lou Y, Yan Z, Zhang F, et al. Comparing through-silicon-via (TSV) void/pinhole defect self-test methods. J Electron Test, 2012, 28: 27-38 CrossRef Google Scholar

Copyright 2019 Science China Press Co., Ltd. 《中国科学》杂志社有限责任公司 版权所有

京ICP备18024590号-1