logo

SCIENTIA SINICA Informationis, Volume 48, Issue 6: 701-712(2018) https://doi.org/10.1360/N112018-00009

Design of communication architecture for flexible electronic system based on honeycomb

More info
  • ReceivedJan 8, 2018
  • AcceptedMar 27, 2018
  • PublishedJun 6, 2018

Abstract

In recent years, the emergence of flexible electronics has led to the rapid development of wearable devices, medical electronics, flexible displays, and the Internet of Things. With the increasing complexity of flexible electronics, more and more functional devices are integrated on flexible substrates. Communication between functional devices has become one of the most important issues in flexible electronics design. In this paper, we proposed a novel communication architecture of flexible electronic system based on a honeycomb structure and novel routing algorithm. Compared to the traditional structure, the proposed structure can effectively avoid the rupture of interconnections caused by excessive local deformation. Compared to the mesh network-on-chip, the area and power consumption of the proposed communication architecture are reduced by 46.43% and 30.51%, respectively.


Funded by

国家重点基础研究发展计划(2015CB351906)

高等学校学科创新引智计划(B12026)


References

[1] Feng X, Lu B W, Wu J, et al. Review on stretchable and flexible inorganic electronics. Acta Phy Sin, 2014, 63: 014201. Google Scholar

[2] Gupta U, Ogras U Y. Extending networks from chips to flexible and stretchable electronics. In: Proceedings of the 10th IEEE/ACM International Symposium on Networks-on-Chip, Nara, 2016. Google Scholar

[3] Gonzalez M, Vandevelde B, Christiaens W. Design and implementation of flexible and stretchable systems. Microelectron Reliab, 2011, 51: 1069-1076 CrossRef Google Scholar

[4] Gonzalez M, Axisa F, Bossuyt F, et al. Design and performance of metal conductors for stretchable electronic circuits. In: Proceedings of the 2nd Electronics System-Integration Technology Conference, Greenwich, 2008. 371--376. Google Scholar

[5] Gonzalez M, Axisa F, Bulcke M V, et al. Design of metal interconnects for stretchable electronic circuits using finite element analysis. In: Proceedings of International Conference on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems, London, 2007. Google Scholar

[6] Council N R. Flexible Electronics for Security, Manufacturing, and Growth in the United States: Summary of A Symposium. Washington: The National Academies Press, 2013. Google Scholar

[7] Kim D H, Ahn J H, Choi W M. Stretchable and foldable silicon integrated circuits. Science, 2008, 320: 507-511 CrossRef PubMed ADS Google Scholar

[8] Kim D H, Song J, Choi W M. From the cover: materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations. Proc Natl Acad Sci USA, 2008, 105: 18675-18680 CrossRef PubMed ADS Google Scholar

[9] Yoon J, Baca A J, Park S I. Ultrathin silicon solar microcells for semitransparent, mechanically flexible and microconcentrator module designs. Nat Mater, 2008, 7: 907-915 CrossRef PubMed ADS Google Scholar

[10] Kim D H, Kim Y S, Wu J. Ultrathin silicon circuits with strain-isolation layers and mesh layouts for high-performance electronics on fabric, vinyl, leather, and paper. Adv Mater, 2009, 21: 3703-3707 CrossRef Google Scholar

[11] Chang R F, Feng X, Chen W Q. Mechanics designs for stretchable inorganic electronics. Chin Sci Bull, 2015, 60: 2079-2090 CrossRef Google Scholar

[12] Guerrier P, Greiner A. A generic architecture for on-chip packet-switched interconnections. In: Proceedings of Design, Automation and Test in Europe Conference and Exhibition, Paris, 2000, 250--256. Google Scholar

[13] Pande P P, Grecu C, Ivanov A, et al. Design of a switch for network on chip applications. In: Proceedings of International Symposium on Circuits and Systems, Bangkok, 2003. Google Scholar

[14] Kumar S, Jantsch A, Soininen J P, et al. A network on chip architecture and design methodology. In: Proceedings IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, 2002. 105--112. Google Scholar

[15] Dally W J, Towles B. Route packets, not wires: on-chip interconnection networks. In: Proceedings of the 38th Design Automation Conference, Las Vegas, 2001, 684--689. Google Scholar

[16] Karim F, Nguyen A, Dey S. An interconnect architecture for networking systems on chips. IEEE Micro, 2002, 22: 36-45 CrossRef Google Scholar

[17] Coppola M, Locatelli R, Maruccia G, et al. Spidergon: a novel on-chip communication network. In: Proceedings of International Symposium on System-on-Chip, Tampere, 2004. Google Scholar

[18] Jiang N, Balfour J, Becker D U, et al. A detailed and flexible cycle-accurate network-on-chip simulator. In: Proceedings of International Symposium on Performance Analysis of Systems and Software (ISPASS), Austin, 2013, 86--96. Google Scholar

[19] Kahng A B, Lin B, Nath S. ORION3.0: a comprehensive NoC router estimation tool. IEEE Embedded Syst Lett, 2015, 7: 41-45 CrossRef Google Scholar

[20] Dally W, Towles B. Principles and Practices of Interconnection Networks. San Francisco: Morgan Kaufmann Publishers, 2004. Google Scholar

  • Figure 1

    Diagram of a flexible and stretchable electronic system

  • Figure 2

    (Color online) Diagram of island-bridge structure

  • Figure 3

    Diagram of flexible and stretchable electronic system based on network-on-chip

  • Figure 4

    (Color online) Diagram of the communication architecture of honeycomb network-on-chip (a) and the structure model of honeycomb network-on-chip (b)

  • Figure 5

    (Color online) Stress and strain distribution of the honeycomb network-on-chip when tension is 10%. (a) Overall stress distribution; (b) overall strain distribution

  • Figure 6

    (Color online) Stress and strain distribution of the honeycomb network-on-chip when compression is 10%.protect łinebreak (a) Overall stress distribution; (b) overall strain distribution

  • Figure 7

    (Color online) Stress and strain distribution of the honeycomb network-on-chip when it is bent. (a) Overall stress distribution; (b) overall strain distribution

  • Figure 8

    Diagram of different topologies. (a) SPIN; (b) BFT; (c) Mesh; (d) Torus; (e) Octagon; (f) Spidergon

  • Figure 9

    (Color online) Diagram of routing algorithm in honeycomb network-on-chip

  • Figure 10

    Turn model of routers. (a) Turn model of routers on odd node; (b) turn model of routers on even node

  •   

    Algorithm 1 Routing algorithm OEXY

    Require:$C$(Xc,Yc), $D$(Xd,Yd);

    while (Xc,Yc) $\neq$ (Xd,Yd) do

    if Xc is odd then

    if Yc $>$ Yd then

    Go down;

    Yc = Yc $-$ 1;

    else

    if Xc $<$ Xd then

    Turn right;

    Xc = Xc $+$ 1;

    else

    Turn left;

    Xc = Xc $-$ 1;

    end if

    end if

    else

    if Yc $<$ Yd then

    Go up;

    Yc = Yc $+$ 1;

    else

    if Xc $<$ Xd then

    Turn right;

    Xc = Xc $+$ 1;

    else

    Turn left;

    Xc = Xc $-$ 1;

    end if

    end if

    end if

    end while

    Output: Output port of the router.

  • Table 1   Comparison of the parameters of different topologies
    Topology IPs Routers Node degree Diameter Links
    SPIN [12] $N$ $3N/4~(N\geqslant64)$ 4 $N/8$ $7N/2~(N\geqslant64)$
    BFT [13] $N$ $N/2$ 6 $N/8$ $2N$
    Mesh [14] $N$ $N$ 5 $2(\sqrt{N}-1)$ $3N-2\sqrt{N}$
    Torus [15] $N$ $N$ 5 $2[\sqrt{N}/2]$ $3N$
    Octagon [16] $N$ $N$ 7 $[N/4]$ $({\rm~Nmod}(8)+1)~\times~20$
    Spidergon [17] $N$ $N$ 4 $[N/4]$ $5N/2$
    Proposed $N$ $N$ 4 $[5\sqrt{N}/2]-3$ $5N/2$
  • Table 2   Basic parameters of different topologies
    Topology IPs Routers Length of message (flits) Depth of buffer (flits) Routing algorithm
    SPIN [12] 16 8 32 2 NCA [18]
    BFT [13] 16 6 32 2 NCA [18]
    Mesh [14] 16 16 32 2 XY [18]
    Torus [15] 16 16 32 2 Adapt_XY [18]
    Octagon [16] 16 16 32 2 Adapt_min [18]
    Spidergon [17] 16 16 32 2 Adapt_min [18]
    Proposed 16 16 32 2 Proposed
  • Table 3   Comparison of the area of different topologies
    Area ($\mu$m$^{2}$) SPIN BFT Mesh Torus Octagon Spidergon Proposed
    Channel 0.04 0.03 0.05 0.09 0.05 0.05 0.04
    Switch 0.13 0.05 0.17 0.17 0.11 0.11 0.07
    Input FIFO 0.03 0.02 0.05 0.05 0.04 0.04 0.03
    Output FIFO 0.01 0.01 0.01 0.01 0.01 0.01 0.01
    Total [16] 0.21 0.11 0.28 0.32 0.21 0.20 0.15
  • Table 4   Comparison of the power comsumption of different topologies
    Power (mW) SPIN BFT Mesh Torus Octagon Spidergon Proposed
    Channel wire power 15.28 11.97 18.66 26.03 13.40 11.51 13.59
    Channel clock power 0.48 0.36 0.73 1.21 0.62 0.61 0.52
    Channel retiming power 0.19 0.15 0.23 0.32 0.17 0.14 0.17
    Channel leakage power 0.18 0.14 0.27 0.46 0.23 0.23 0.19
    Input read power 0.29 0.21 0.39 0.35 0.28 0.24 0.29
    Input write power 0.29 0.21 0.39 0.35 0.28 0.24 0.29
    Input leakage power 0.03 0.02 0.05 0.05 0.04 0.04 0.03
    Switch power 2.04 0.78 1.82 1.66 1.02 0.84 0.86
    Switch control power 0.71 0.30 0.69 0.62 0.43 0.34 0.36
    Switch leakage power 0.49 0.13 0.47 0.47 0.28 0.26 0.16
    Output DFF power 0.07 0.05 0.09 0.08 0.06 0.06 0.07
    Output Clk power 0.18 0.12 0.30 0.30 0.25 0.24 0.20
    Output control power 0.04 0.03 0.05 0.04 0.03 0.03 0.04
    Total power 20.27 14.47 24.12 31.94 17.10 14.77 16.76

Copyright 2019 Science China Press Co., Ltd. 《中国科学》杂志社有限责任公司 版权所有

京ICP备18024590号-1