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SCIENTIA SINICA Informationis, Volume 48, Issue 8: 963-977(2018) https://doi.org/10.1360/N112018-00114

Device and integration technologies for VLSI in post-Moore era

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  • ReceivedApr 18, 2018
  • AcceptedMay 28, 2018
  • PublishedAug 6, 2018

Abstract

We herein review the technology transition from thescaling-driven technical roadmap to the power-driven post-Moore roadmap,focusing on the primary trend in micro/nanoelectronics devices. Thenovel devices and process integration technologies in post-Moore era, suchas the FinFET, gate-all-around transistor, tunneling FET, and the sequential 3Dintegration process were systematically analyzed to provide newinsights into the everlasting evolution of VLSI technology.


Funded by

国家重点研发计划(2016YFA0200504)

国家自然科学基金(61474004,61421005)


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  • 1   Table 1Comparison of three main formation schemes of active layer for topdevices
    Scheme Laser+CMP Solid phase epitaxy Bonding
    Diagrams

    Process temperature ($^{\circ}$C) $\sim~25$ (GNS-LC) $\sim~650$ (SEG) $\sim~200$
    Quality of recrystallization Random distribution of defects Limited defects in seed-window Ideal
    Orientation control Same as seed Not specified Designable

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