logo

SCIENTIA SINICA Informationis, Volume 50, Issue 2: 163-183(2020) https://doi.org/10.1360/SSI-2019-0207

Research progress in Ge-based advanced field effect transistor technology

More info
  • ReceivedSep 24, 2019
  • AcceptedOct 31, 2019
  • PublishedFeb 11, 2020

Abstract

The modern integrated circuit is among the world's mostcomplex systems, but at its heart is a very simple, and we think beautiful,device: the transistor. Right now, 7 nm process technology is the cutting edge in traditional silicon-based integrated-circuit-manufacturing industry. However,the downscaling of the technological node in accordance with Moore's Law is becomingincreasingly difficult, not to mention fantastically expensive. Ge has beenconsidered a promising channel material due its high hole andelectron motilities, which facilitate the drive-current boost withoutdownscaling the device's dimensions. This paper summaries the current state-of-the-art Gemetal-oxide-semiconductor field-effect transistors (MOSFETs) from these three angles: gate stacks, source/drainformation, and new device structure. It is found that many criticalphysical and engineering problems concerning Ge MOSFETs are still under discussion, including basic device fabrication and the deep physicalunderstanding of Ge MOSFETs. Nevertheless, Ge MOSFETs reported by bothacademic and industrial researchers show superior performance totraditional Si MOSFETs, suggesting that Ge is a promising material for future high-performance complementary-MOS (CMOS) devices under 3 nm node.


Funded by

浙江省自然科学基金重点项目(Z19F040002)

浙江省重点研发计划(2019C01158)


References

[1] Narasimha S, Jagannathan B, Ogino A, et al. A 7 nm CMOS technology platform for mobile and high performance compute application. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2017. 1--4. Google Scholar

[2] Auth C, Aliyarukunju A, Asoro M, et al. A 10 nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, self-aligned quad patterning, contact over active gate and cobalt local interconnects. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2017. 1--4. Google Scholar

[3] Kuhn K J. Considerations for Ultimate CMOS Scaling. IEEE Trans Electron Devices, 2012, 59: 1813-1828 CrossRef Google Scholar

[4] Natarajan S, Agostinelli M, Akbar S, et al. A 14 nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 $\mu~$m$^{2}$, SRAM cell size. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2015. 1--3. Google Scholar

[5] Chan V, Rengarajan R, Rovedo N, et al. High speed 45 nm gate length CMOSFETs integrated into a 90 nm bulk technology incorporating strain engineering. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2003. 77--80. Google Scholar

[6] Collaert N. Novel channel materials for high-performance and low-power CMOS, In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2016. Google Scholar

[7] International Technology Roadmap for Semiconductors (ITRS), 2013 version. Google Scholar

[8] Matsubara H, Sasada T, Takenaka M. Evidence of low interface trap density in GeO2?MGe metal-oxide-semiconductor structures fabricated by thermal oxidation. Appl Phys Lett, 2008, 93: 032104 CrossRef Google Scholar

[9] Ma J, Zhang W D, Zhang J F. IEEE Trans Electron Devices, 2016, 63: 3830-3836 CrossRef Google Scholar

[10] Lin L, Xiong K, Robertson J. Atomic structure, electronic structure, and band offsets at Ge:GeO:GeO2 interfaces. Appl Phys Lett, 2010, 97: 242902 CrossRef Google Scholar

[11] Choong Hyun Lee , Nishimura T, Nagashio K. High-Electron-Mobility $\hbox{Ge/GeO}_{2}$ n-MOSFETs With Two-Step Oxidation. IEEE Trans Electron Devices, 2011, 58: 1295-1301 CrossRef Google Scholar

[12] Zhang R, Huang P C, Taoka N, et al. High mobility Ge pMOSFETs with 0.7 nm ultrathin EOT using HfO2/Al$_{2}$O$_{3}$/GeO$_x$/Ge gate stacks fabricated by plasma post oxidation. In: Proceedings of IEEE Symposium on VLSI Technology, Kyoto, 2011. 161--162. Google Scholar

[13] Zhang R, Tang X, Yu X. IEEE Electron Device Lett, 2016, 37: 831-834 CrossRef Google Scholar

[14] Sun J B, Yang Z W, Geng Y, et al. Equivalent oxide thickness scaling of Al$_{2}$O$_{3}$/Ge metal-oxide-semiconductor capacitors with ozone post oxidation. Chinese Physics B, 2013, 22: 561-564. Google Scholar

[15] Zhang R, Iwasaki T, Taoka N. High-Mobility Ge pMOSFET With 1-nm EOT $\hbox{Al}_{2}~\hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}$ Gate Stack Fabricated by Plasma Post Oxidation. IEEE Trans Electron Devices, 2012, 59: 335-341 CrossRef Google Scholar

[16] Zhang R, Li J, Yu X. IEEE Trans Electron Devices, 2017, 64: 4831-4837 CrossRef Google Scholar

[17] Zhang R, Lin J C, Yu X. Impact of Plasma Postoxidation Temperature on the Electrical Properties of ${\rm~~Al}_{2}{\rm~~O}_{3}/{\rm~~GeO}_{x}/{\rm~~Ge}$ pMOSFETs and nMOSFETs. IEEE Trans Electron Devices, 2014, 61: 416-422 CrossRef Google Scholar

[18] Zhang R, Taoka N, Huang P C, et al. 1-nm-thick EOT high mobility Ge n- and p-MOSFETs with ultrathin GeOx/Ge MOS interfaces fabricated by plasma post oxidation. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2011. 1--4. Google Scholar

[19] Shang H, Frank M M, Gusev E P. Germanium channel MOSFETs: Opportunities and challenges. IBM J Res Dev, 2006, 50: 377-386 CrossRef Google Scholar

[20] Zhang R, Iwasaki T, Taoka N. Suppression of ALD-Induced Degradation of Ge MOS Interface Properties by Low Power Plasma Nitridation of GeO2. J Electrochem Soc, 2011, 158: G178 CrossRef Google Scholar

[21] Lee C H, Nishimura T, Tabata T, et al. Ge MOSFETs performance: impact of Ge interface passivation. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2010. 1--4. Google Scholar

[22] Lee C H, Lu C, Tabata T, et al. Oxygen potential engineering of interfacial layer for deep sub-nm EOT high-k gate stacks on Ge. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2013. 1--4. Google Scholar

[23] Arimura H, Sioncke S, Cott D, et al. Ge nFET with high electron mobility and superior PBTI reliability enabled by monolayer-Si surface passivation and La-induced interface dipole formation. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2015. 1--4. Google Scholar

[24] Dal M J H V. Demonstration of scaled Ge p-channel FinFETs integrated on Si. International Journal for Parasitology. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2012. 1--4. Google Scholar

[25] Pillarisetty R, Chu-Kung B, Corcoran S, et al. High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc= 0.5 V) III--V CMOS architecture. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2010. 1--4. Google Scholar

[26] Kobabyashi M, Mitard J, Irisawa T, et al. Experimental demonstration of high source velocity and its enhancement by uniaxial stress in Ge PFETs. In: Proceedings of IEEE Symposium on VLSI Technology, Honolulu, 2010. 215--216. Google Scholar

[27] Gong X, Zhou Q, Owen M H S, et al. InAlP-Capped (100) Ge nFETs with 1.06 nm EOT: achieving record high peak mobility and first integration on 300 mm Si substrate. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2014. 231--234. Google Scholar

[28] Liu B, Gong X, Cheng R, et al. High performance Ge CMOS with novel InAlP-passivated channels for future sub-10 nm technology node applications. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2013. 657--659. Google Scholar

[29] Li J, Xie S, Zheng Z, et al. High performance and reliability Ge channel CMOS with a MoS$_{2}$ capping layer. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2017. 830--833. Google Scholar

[30] Huang Y S, Tsou Y J, Huang C H. IEEE Trans Electron Devices, 2017, 64: 2498-2504 CrossRef Google Scholar

[31] Hashemi P, Hoyt J L. High Hole-Mobility Strained-$\hbox{Ge/Si}_{0.6}~\hbox{Ge}_{0.4}$ P-MOSFETs With High-K/Metal Gate: Role of Strained-Si Cap Thickness. IEEE Electron Device Lett, 2012, 33: 173-175 CrossRef Google Scholar

[32] Zhou J, Han G, Peng Y. Ferroelectric Negative Capacitance GeSn PFETs With Sub-20 mV/decade Subthreshold Swing. IEEE Electron Device Lett, 2017, 38: 1157-1160 CrossRef Google Scholar

[33] Su C, Hong T, Tsou Y, et al. Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2017. 1--4. Google Scholar

[34] Si M W, Jiang C S, Su C J, et al. Sub-60 mV/dec ferroelectric HZO MoS2 negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2017. 1--4. Google Scholar

[35] Si M, Su C J, Jiang C, et al. Steep-slope hysteresis-free negative capacitance MoS$_{2}$ transistors. Nat Nanotechnol, 2018, 12: 24--28. Google Scholar

[36] Chung W, Si M, Ye P D. Hysteresis-free negative capacitance germanium CMOS FinFETs with Bi-directional Sub-60 mV/dec. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2017. 1--4. Google Scholar

[37] Trumbore F A. Solid Solubilities of Impurity Elements in Germanium and Silicon*. Bell Syst Technical J, 1960, 39: 205-233 CrossRef Google Scholar

[38] Chroneos A, Bracht H. Appl Phys Rev, 2014, 1: 011301 CrossRef Google Scholar

[39] Zhang Q, Huang J, Wu N. Drive-Current Enhancement in Ge n-Channel MOSFET Using Laser Annealing for Source/Drain Activation. IEEE Electron Device Lett, 2006, 27: 728-730 CrossRef Google Scholar

[40] Chen W B, Wu C H, Shie B S. Gate-First $\hbox{TaN/La}_{2}\hbox{O}_{3}/~\hbox{SiO}_{2}/\hbox{Ge}$ n-MOSFETs Using Laser Annealing. IEEE Electron Device Lett, 2010, CrossRef Google Scholar

[41] Chen W B, Shie B S, Chin A, et al. Higher $k$ metal-gate/high-$k$ /Ge n-Mosfets with $<1$ nm EOT ssing laser annealing. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2010. 1--4. Google Scholar

[42] Li J, Cheng R, Liu C, et al. High performance Ge ultra-shallow junctions fabricated by a novel formation technique featuring spin-on dopant and laser annealing for sub-10 nm technology applications. Microelectronic Engineering, 2017, 168: 1-4. Google Scholar

[43] Yamamoto T, Yamashita Y, Harada M, et al. High performance 60 nm gate length germanium p-MOSFETs with Ni germanide metal source/drain. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2007. 1041--1043. Google Scholar

[44] Yokoyama M, Kim S H, Zhang R, et al. CMOS integration of InGaAs nMOSFETs and Ge pMOSFETs with self-align Ni-based metal S/D using direct wafer bonding. In: Proceedings of IEEE Symposium on VLSI Technology, Honolulu, 2011. 60--61. Google Scholar

[45] Li R, Yao H B, Lee S J. Metal-germanide Schottky Source/Drain transistor on Germanium substrate for future CMOS technology. Thin Solid Films, 2006, 504: 28-31 CrossRef Google Scholar

[46] Che-Wei Chen , Ju-Yuan Tzeng , Cheng-Ting Chung . High-Performance Germanium p- and n-MOSFETs With NiGe Source/Drain. IEEE Trans Electron Devices, 2014, 61: 2656-2661 CrossRef Google Scholar

[47] Shiyang Zhu , Rui Li , Lee S J. Germanium pMOSFETs with Schottky-barrier germanide S/D, high-/spl kappa/ gate dielectric and metal gate. IEEE Electron Device Lett, 2005, 26: 81-83 CrossRef Google Scholar

[48] Zhang R, Li J, Chen F. High-Performance Germanium pMOSFETs With NiGe Metal Source/Drain Fabricated by Microwave Annealing. IEEE Trans Electron Devices, 2016, 63: 2665-2670 CrossRef Google Scholar

[49] Nishimura T, Kita K, Toriumi A. Evidence for strong Fermi-level pinning due to metal-induced gap states at metal/germanium interface. Appl Phys Lett, 2007, 91: 123123 CrossRef Google Scholar

[50] Ikeda K, Yamashita Y, Sugiyama N. Modulation of NiGe?MGe Schottky barrier height by sulfur segregation during Ni germanidation. Appl Phys Lett, 2006, 88: 152115 CrossRef Google Scholar

[51] Li Z, An X, Li M. Low Electron Schottky Barrier Height of NiGe/Ge Achieved by Ion Implantation After Germanidation Technique. IEEE Electron Device Lett, 2012, 33: 1687-1689 CrossRef Google Scholar

[52] Mueller M, Zhao Q T, Urban C. Schottky-barrier height tuning of NiGe/n-Ge contacts using As and P segregation. Mater Sci Eng-B, 2008, 154-155: 168-171 CrossRef Google Scholar

[53] Chen C W, Tzeng J Y, Chung C T. Enhancing the Performance of Germanium Channel nMOSFET Using Phosphorus Dopant Segregation. IEEE Electron Device Lett, 2014, 35: 6-8 CrossRef Google Scholar

[54] Chang W H, Irisawa T, Ishii H, et al. Ion implantation after germanidation technique for low thermal budget Ge CMOS devices: from bulk Ge to UTB-GeOI substrate. In: Proceedings of International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, 2017. Google Scholar

[55] Modulation of NiGe/Ge Schottky barrier height by S and P co-introduction. Appl Phys Lett, 2013, 102: 032108 CrossRef Google Scholar

[56] Tsui B Y, Shih J J, Lin H C. A study on NiGe-contacted Ge n+/p Ge shallow junction prepared by dopant segregation technique. Solid-State Electron, 2015, 107: 40-46 CrossRef Google Scholar

[57] Duan N, Luo J, Wang G. Reduction of NiGe/n- and p-Ge Specific Contact Resistivity by Enhanced Dopant Segregation in the Presence of Carbon During Nickel Germanidation. IEEE Trans Electron Devices, 2016, 63: 4546-4549 CrossRef Google Scholar

[58] Yang B, Lin J Y J, Gupta S, et al. Low-contact-resistivity nickel germanide contacts on n+ Ge with phosphorus/antimony co-doping and Schottky barrier height lowering. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2012. 1--2. Google Scholar

[59] Wang L L, Yu H, Schaekers M, et al. Comprehensive study of Ga activation in Si, SiGe and Ge with $5\times~10^{-10}~~\Omega$-cm$^{2}$ contact resistivity achieved on Ga doped Ge using nanosecond laser activation. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2017. 1--4. Google Scholar

[60] Wu Y, Chua L H, Wang W, et al. Sub-10$^{~-~9}~~~\Omega~$-cm$^{2}$ Specific Contact Resistivity on P-type Ge and GeSn: In-situ Ga Doping with Ga Ion Implantation at 300$^\circ$C, 25$^\circ$C, and $-$100$^\circ$C. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2018. 1--4. Google Scholar

[61] Kobayashi M, Kinoshita A, Saraswat K, et al. Fermi-level depinning in metal/Ge Schottky junction and its application to metal source/drain Ge NMOSFET. In: Proceedings of IEEE Symposium on VLSI Technology, Honolulu, 2008. 54--55. Google Scholar

[62] Jason Lin J Y, Roy A M, Saraswat K C. Reduction in Specific Contact Resistivity to $~\hbox{n}^{+}$ Ge Using $\hbox{TiO}_{2}$ Interfacial Layer. IEEE Electron Device Lett, 2012, 33: 1541-1543 CrossRef Google Scholar

[63] Iyota M, Yamamoto K, Wang D. Ohmic contact formation on n-type Ge by direct deposition of TiN. Appl Phys Lett, 2011, 98: 192108 CrossRef Google Scholar

[64] Wu H D, Huang W, Lu W F. Ohmic contact to n-type Ge with compositional Ti nitride. Appl Surf Sci, 2013, 284: 877-880 CrossRef Google Scholar

[65] Wu H, Luo W, Si M, et al. Deep sub-100 nm Ge CMOS devices on Si with the recessed S/D and channel. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2014. 1--4. Google Scholar

[66] Wu H, Conrad N, Luo W, et al. First experimental demonstration of Ge CMOS circuits. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2014. 1--4. Google Scholar

[67] Kim S H, Kam H, Hu C, et al. Germanium-source tunnel field effect transistors with record high ION/IOFF. In: Proceedings of IEEE Symposium on VLSI Technology, Honolulu, 2009. 178--179. Google Scholar

[68] Yang Y, Su S, Guo P, et al. Towards direct band-to-band tunneling in p-channel tunneling field effect transistor (TFET): Technology enablement by germanium-tin (GeSn). In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2012. 1--4. Google Scholar

[69] Yang Y, Han G, Guo P. Germanium-Tin P-Channel Tunneling Field-Effect Transistor: Device Design and Technology Demonstration. IEEE Trans Electron Devices, 2013, 60: 4048-4056 CrossRef Google Scholar

[70] Nah J, Liu E S, Varahramyan K M. Enhanced-Performance Germanium Nanowire Tunneling Field-Effect Transistors Using Flash-Assisted Rapid Thermal Process. IEEE Electron Device Lett, 2010, 31: 1359-1361 CrossRef Google Scholar

[71] Luong G V, Narimani K, Tiedemann A T. Complementary Strained Si GAA Nanowire TFET Inverter With Suppressed Ambipolarity. IEEE Electron Device Lett, 2016, 37: 950-953 CrossRef Google Scholar

[72] Li J, Qu Y, Zeng S. Ge Complementary Tunneling Field-Effect Transistors Featuring Dopant Segregated NiGe Source/Drain. Chin Phys Lett, 2018, 35: 117201 CrossRef Google Scholar

[73] Avci U E, Chu-Kung B, Agrawal A, et al. Study of TFET non-ideality effects for determination of geometry and defect density requirements for sub-60mV/dec Ge TFET. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2015. 1--4. Google Scholar

[74] Togo M, Lee J W, Pantisano L, et al. Phosphorus doped SiC source drain and SiGe channel for scaled bulk FinFETs. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2012. 1--4. Google Scholar

[75] Hashemi P, Kobayashi M, Majumdar A, et al. High-performance Si$_{1~-~x}$Ge$_{x}$ channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions. In: Proceedings of IEEE Symposium on VLSI Technology, Kyoto, 2013. 18--19. Google Scholar

[76] Mertens H, Ritzenthaler R, Hikavyy A, et al. Performance and reliability of high-mobility Si$_{0.55}$Ge$_{0.45}$ p-channel FinFETs based on epitaxial cladding of Si Fins. In: Proceedings of IEEE Symposium on VLSI Technology, Honolulu, 2014. 1--2. Google Scholar

[77] Hashemi P, Balakrishnan K, Majumdar A, et al. Strained Si$_{1~-~x}$Ge$_{x}$-on-insulator PMOS FinFETs with excellent sub-threshold leakage, extremely-high short-channel performance and source injection velocity for 10nm node and beyond. In: Proceedings of IEEE Symposium on VLSI Technology, Honolulu, 2014. 1--2. Google Scholar

[78] Hashemi P, Balakrishnan K, Engelmann S U, et al. First demonstration of high-Ge-content strained- Si$_{1-x}$Ge$_{x}$ ($x=~0.5$) on insulator PMOS FinFETs with high hole mobility and aggressively scaled fin dimensions and gate lengths for high-performance applications. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2014. 1--4. Google Scholar

[79] Hashemi P, Ando T, Balakrishnan K, et al. High-mobility high-Ge-content Si1$~-~$xGex-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x$~\sim~$0.7, scaled EOT$~\sim~$ 8.5 Å and$~\sim~$ 10nm fin width. In: Proceedings of IEEE Symposium on VLSI Technology, Kyoto, 2015. 16--17. Google Scholar

[80] Hashemi P, Ando T, Balakrishnan K, et al. Replacement high-K/metal-gate High-Ge-content strained SiGe FinFETs with high hole mobility and excellent SS and reliability at aggressive EOT$~\sim~$7 Å and scaled dimensions down to sub-4nm fin widths. In: Proceedings of IEEE Symposium on VLSI Technology, Honolulu, 2016. 1--2. Google Scholar

[81] Hashemi P, Lee K L, Ando T, et al. Demonstration of record SiGe transconductance and short-channel current drive in High-Ge-Content SiGe PMOS FinFETs with improved junction and scaled EOT. In: Proceedings of IEEE Symposium on VLSI Technology, Honolulu, 2016. 1--2. Google Scholar

[82] Guo D, Karve G, Tsutsui G, et al. FINFET technology featuring high mobility SiGe channel for 10nm and beyond. In: Proceedings of IEEE Symposium on VLSI Technology, Honolulu, 2016. 1--2. Google Scholar

[83] Lee C H, Southwick R G, Mochizuki S, et al. Toward high performance SiGe channel CMOS: design of high electron mobility in SiGe nFinFETs outperforming Si. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2018. 1--4. Google Scholar

[84] Van Dal M J H, Vellianitis G, Doornbos G, et al. Demonstration of scaled Ge p-channel FinFETs integrated on Si. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2012. 1--4. Google Scholar

[85] Duriez B, Vellianitis G, van Dal M J H, et al. Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300 mm Si wafers. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2013. 1--4. Google Scholar

[86] Liu B, Gong X, Cheng R, et al. High performance Ge CMOS with novel InAlP-passivated channels for future sub-10 nm technology node applications. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2013. 1--3. Google Scholar

[87] Witters L, Mitard J, Loo R, et al. Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2013. 1--4. Google Scholar

[88] Agrawal A, Barth M, Rayner G B, et al. Enhancement mode strained (1.3 germanium quantum well FinFET ($W_{\rm~~Fin}=~20$ nm) with high mobility ($\mu~_{\rm~~Hole}=$ 700 cm$^{2}$/Vs), low EOT ($\sim~$0.7 nm) on bulk silicon substrate. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2014. 1--4. Google Scholar

[89] Mitard J, Witters L, Arimura H, et al. First demonstration of 15 nm-W FIN inversion-mode relaxed-Germanium n-FinFETs with Si-cap free RMG and NiSiGe Source/Drain. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2014. 1--4. Google Scholar

[90] Mitard J, Witters L, Sasaki Y, et al. A 2nd Generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs. In: Proceedings of IEEE Symposium on VLSI Technology, Honolulu, 2016. 1--2. Google Scholar

[91] Wu H, Luo W, Zhou H, et al. First experimental demonstration of Ge 3D FinFET CMOS circuits. In: Proceedings of IEEE Symposium on VLSI Technology, Kyoto, 2015. 58--59. Google Scholar

[92] Hyun Lee C, Nishimura T, Tabata T. Characterization of electron mobility in ultrathin body germanium-on-insulator metal-insulator-semiconductor field-effect transistors. Appl Phys Lett, 2013, 102: 232107 CrossRef Google Scholar

[93] Yu X, Kang J, Takenaka M, et al. Experimental study on carrier transport properties in extremely-thin body Ge-on-insulator (GOI) p-MOSFETs with GOI thickness down to 2 nm. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2015. 1--4. Google Scholar

[94] Kim W K, Takenaka M, Takagi S. High performance 4.5-nm-thick compressively-strained Ge-on-insulator pMOSFETs fabricated by Ge condensation with optimized temperature control. In: Proceedings of IEEE Symposium on VLSI Technology, Kyoto, 2017. 124--125. Google Scholar

[95] Chang W H, Irisawa T, Ishii H, et al. First experimental observation of channel thickness scaling (down to 3 nm) induced mobility enhancement in UTB GeOI nMOSFETs. In: Proceedings of IEEE Symposium on VLSI Technology, Kyoto, 2017. 192--193. Google Scholar

[96] Zheng Z, Yu X, Zhang Y. Back-Gate Modulation in UTB GeOI pMOSFETs With Advanced Substrate Fabrication Technique. IEEE Trans Electron Devices, 2018, 65: 895-900 CrossRef Google Scholar

[97] Cheng R, Liu B, Guo P, et al. Asymetrically strained high performance germanium gate-all-around nanowire p-FETs featuring 3.5 nm wire width and contractible phase change liner stressor (Ge$_{2}$Sb$_{2}$Te$_{5})$. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2013. 1--4. Google Scholar

[98] Mertens H, Ritzenthaler R, Arimura H, et al. Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: interface trap density reduction and performance improvement by high-pressure deuterium anneal. In: Proceedings of IEEE Symposium on VLSI Technology, Kyoto, 2015. 142--143. Google Scholar

[99] Loubet N, Hook T, Montanini P, et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. In: Proceedings of IEEE Symposium on VLSI Technology, Kyoto, 2017. 230--231. Google Scholar

Copyright 2020 Science China Press Co., Ltd. 《中国科学》杂志社有限责任公司 版权所有

京ICP备18024590号-1