SCIENCE CHINA Information Sciences, Volume 61 , Issue 6 : 060423(2018) https://doi.org/10.1007/s11432-018-9425-1

Artificial neural networks based on memristive devices

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  • ReceivedFeb 22, 2018
  • AcceptedMar 27, 2018
  • PublishedMay 15, 2018


The advent of memristive devices and the continuing researchand development in the field of neuromorphic computing show great potentialas an alternative to traditional von Neumann computing and bring us evercloser to realizing a true “thinking machine”. Novel neural networkarchitectures and algorithms inspired by the brain are becoming more andmore attractive to keep up with computing needs, relying on intrinsicparallelism and reduced power consumption to outperform more conventionalcomputing methods. This article provides an overview of various neuralnetworks with an emphasis on networks based on memristive emerging devices,with the advantages of memristor neural networks compared with purecomplementary metal oxide semiconductor (CMOS) implementations. A generaldescription of neural networks is presented, followed by a survey ofprominent CMOS networks, and finally networks implemented using emergingmemristive devices are discussed, along with the motivation for developingmemristor based networks and the computational potential these networkspossess.


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  • Figure 1

    (Color online) Neuron and synapse structure. (a) Simplified biological structure of pre-synaptic and post-synaptic neurons showing the axon, synapses, and dendrites [6]@Copyright 2017 Scientific Reports; (b) biological synaptic structure and function [7]@Copyright 2011 Frontiers in Neuroscience.

  • Figure 2

    (Color online) (a) Memristor crossbar for vector matrix multiplication (VMM); (b) current (mA) output was experimentally measured for a 6464 crossbar for VMM and the resulting current from column 1 and column 64 were compared with the expected values using software VMM. Non-idealities in the devices and circuitry result in a drastic difference between the ideal output and the actual output [9]@Copyright 2018 Nature Electronics.

  • Figure 3

    (a) ISAAC architecture using tiles [13]. (b) Simplified design of PRIME [14]. External I/O data is fed into RRAM crossbar based banks. Memory subarrays only store data. Full function subarrays can store data or perform computation, using a CMOS controller to enable configuration. The buffer subarrays serve as data buffers for the full function subarrays. (c) AEPE Implementation with efficient tile architecture [15]. The register buffer feeds into M rows of crossbar based PE arrays through an assigned DAC for each row.

  • Figure 4

    (Color online) (a) A single-layer is mapped onto the one transistor one memristor (1T1R) array; (b) micrograph of the 1024 cell 1T1R array fabricated using CMOS compatible processes [16]@Copyright 2017 Nature Communications.

  • Figure 5

    (Color online) (a) Photograph of fabricated 1T1R crossbars. Two dies are shown, each one containing various array sizes from 4$\times$4 to 128$\times$64 cells. (b) Micrograph of four cells in a 1T1R array (scale bar, 10 mm). (c) Relatively linear I-V curves for all the devices over the chosen conductance range. (d) Device state retention and read disturbance (1000 cycles of 0.2 V read pulses) at room temperature show no discernible drift [9]@Copyright 2017 Nature Electronics.

  • Figure 6

    (Color online) (a) Synapse array with peripheral circuitry; (b) a pre-synaptic device controls the FET gate of the 1T1R structure, while the post-synaptic device receives the input current and controls the synapse top electrode to induce synaptic current and stimulate synaptic potentiation or depression during the fire [6]@Copyright 2017 Scientific Reports.

  • Figure 7

    (Color online) Diffusive memristor neuron schematic. The diffusive memristor behaves in a fundamentally similar manner as a biological ion channel on the soma membrane of a neuron [17]@Copyright 2018 Nature Electronics.

  • Figure 8

    (Color online) (a) All memristor network fabricated using (b) and (c) drift memristors for synapses and (d) and (e) diffusive memristors for neurons [17]@Copyright 2018 Nature Electronics.

  • Table 1   Summary of experimental memristor based network implementations presented in literature$^{\rm~a)}$
    ImplementationComputing efficiencyAccuracyPower consumptionMemristor used/Dielectric thicknessCrossbar cell countReference
    1T1R face classifying perceptron networkConverges within 10 iterations88% recognition accuracy within 10 iterations$\sim$30 nJ per epoch for classification taskMemristor-8 nm HfAl$_{y}$O$_{x}$128$\times$8 cells[16]
    1T1R Ta/HfO$_{2}$ memristor network119.7 trillion operations per second per watt91.71% recognition accuracy on MNIST data set13.7 mW for image compressionMemristor-5 nm HfO$_{2}$128$\times$64 cells[9,19,20]
    1T1R STDP networkMemristor-10 nm HfO$_{2}$4$\times$4 pre-cells and 1 post-cell[6]
    Diffusive memristor artificial neuron networkDiffusive memristor-10 nm Ag/SiO$_{2}$ par Drift par Memristor-5 nm HfO$_{2}$8$\times$8 synaptic crossbar with 8 neurons[17]


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