SCIENCE CHINA Information Sciences, Volume 64 , Issue 4 : 149401(2021) https://doi.org/10.1007/s11432-019-2854-9

Simulations of single event effects on the ferroelectric capacitor-based non-volatile SRAM design

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  • ReceivedOct 5, 2019
  • AcceptedMar 18, 2020
  • PublishedNov 19, 2020


There is no abstract available for this article.


This work was supported in part by National Natural Science Foundation of China (Grant No. 616340084).


[1] Miwa T, Yamada J, Koike H. NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors. IEEE J Solid-State Circuits, 2001, 36: 522-527 CrossRef ADS Google Scholar

[2] Kobayashi M, Ueyama N, Jang K. IEEE J Electron Devices Soc, 2018, 6: 280-285 CrossRef Google Scholar

[3] Bi J S, Liu G, Luo J J. Numerical simulation of single-event-transient effects on ultra-thin-body fully-depleted silicon-on-insulator transistor based on 22 nm process node. Acta Physica Sinica, 2013, 62: 504-511 doi: 10.7498/aps.62.208501. Google Scholar

[4] Bi J S, Xi K, Li B. Heavy ion induced upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory. Chin Phys B, 2018, 27: 098501 CrossRef ADS Google Scholar

[5] Wang J J, Bi J S, Bai H, et al. CMOS-compatible ${\rm~~Hf_{0.5}Zr_{0.5}O_2}$-based ferroelectric capacitors for negative capacitance and non-volatile application. In: Proceedings of the 2018 14th IEEE International Conference on Solid-state $\&$ Integrated CircuitsTechnology, 2018. Google Scholar

[6] Wang J J, Bi J S, Bai H, et al. Simulation macro-model for ${\rm~~Hf_{0.5}Zr_{0.5}O_2}$-based ferroelectric capacitor. In: Proceedings of the 2020 33th IEEE International Conference on Microelectronic Test Structures, 2020. Google Scholar

[7] Buchner S, McMorrow D. Single-Event Transients in Bipolar Linear Integrated Circuits. IEEE Trans Nucl Sci, 2006, 53: 3079-3102 CrossRef ADS Google Scholar

  • Figure 1

    (Color online) Simulation results of single event effects of nvSRAM in different operating states. (a) Flowchart for building the FeCap model; (b) experimental results and macro-model simulation results for FeCap at different voltages; (c) independent double exponential current pulses; (d) 6T2C nvSRAM simulation with a peripheral circuit; (e) schematic of the timing chart of the nvSRAM operation; (f) double exponential pulses at $T~=~555$ ns and 560 ns in the “power-off" state; (g) double exponential current pulses with different LET values in the “store" state; (h) threshold LET values under different operating states; (i) double exponential current pulses applied in the “store" phase under different FeCap model parameters.