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SCIENCE CHINA Information Sciences, Volume 63 , Issue 2 : 122401(2020) https://doi.org/10.1007/s11432-019-9836-9

Vertical SnS$_{\boldsymbol~2}$/Si heterostructure for tunnel diodes

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  • ReceivedJan 23, 2019
  • AcceptedMar 15, 2019
  • PublishedSep 16, 2019

Abstract

Tunneling FET (TFET) is considered as one of the most promising low-power electronic devices, however, suffers from the low drive current. Heterostructure TFET with low effective tunnel barrier height based on traditional 3D materials can obtain large tunnel current but deteriorated off-state current induced by the lattice mismatch. van der Waals heterostructure TFET based on 2D materials can obtain dangling-bond-free interface for suppressed off-state current but face the challenge of controllable and stable doping technology. As the critical building block of the TFET, tunnel diode based on the 2D/3D heterostructure is proposed in this study and experimentally demonstrated. Combination of the pristine interface of 2D materials and matured doping technology in the traditional 3D bulk materials, tunnel diodes based on the 2D/3D heterostructures are expected to realize low leakage current and high on current simultaneously, showing great potential in low-power electronics. The N$^+$ SnS$_2$/P$^+$ Si heterostructure with effective tunnel barrier of 0.17 eV theoretically is considered for the first time and selected as the optimal material platform for tunnel diodes. The N$^+$ SnS$_2$/P$^+$ Si tunnel diode demonstrated experimentally shows the high current density of 1 $\mu$A/$\mu$m$^2$, which is the highest one among the reported tunnel diodes based on the 2D/group IV materials. The tunneling current is also confirmed by low-temperature measurements. This study shows the great potential of the 2D/3D heterostructure for low-power tunneling devices.


Acknowledgment

This work was partly supported by National Natural Science Foundation of China (Grant Nos. 61421005, 61851401, 61822401, 61604006) and the 111 Project (Grant No. B18001).


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  • Figure 1

    (Color online) (a) Schematic view of the vertical 2D/3D tunnel diode. Vertical tunneling occurs across the overlap region between the 2D material and the 3D material. (b) Top view of the vertical 2D/3D tunnel diode.

  • Figure 2

    (Color online) The band diagram of the N$^+$ SnS$_2$/P$^+$ Si tunnel diode. (a) The bandgaps and electronic affinities of Si and SnS$_2$; (b) the equilibrium state; (c) the working state-reverse bias region.

  • Figure 3

    (Color online) The details of the process to fabricate the vertical N$^+$ SnS$_2$/P$^+$ Si tunnel diode. (a) The original Si substrate; (b) ion implantation with BF$_2$$^+$; (c) highly p-doped Si; (d) dry etching to form trenches; (e) CVD of SiO$_2$; (f) CMP of SiO$_2$; (g) HF treatment to remove the residual and native oxide; (h) transfer of SnS$_2$ sheet; (i) formation of contacts.

  • Figure 4

    (Color online) (a) The optical microscope image of the fabricated vertical N$^+$ SnS$_2$/P$^+$ Si tunnel diode; protectłinebreak (b) AFM image of fabricated vertical N$^+$ SnS$_2$/P$^+$ Si tunnel diode; (c) Raman characterization of the SnS$_2$ sheet in the tunnel diode.

  • Figure 5

    (Color online) The electric characteristics of the vertical N$^+$ SnS$_2$/P$^+$ Si tunnel diode. (a) Linear and (b) log current-voltage characteristics.

  • Figure 6

    (Color online) The NDR characteristic of the vertical N$^+$ SnS$_2$/P$^+$ Si tunnel diode. (a) The band diagram in the small forward bias region; (b) the band diagram in the large forward bias region.

  • Figure 7

    (Color online) The temperature characteristic of the vertical N$^+$ SnS$_2$/P$^+$ Si tunnel diode.

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