logo

SCIENCE CHINA Information Sciences, Volume 63 , Issue 10 : 202401(2020) https://doi.org/10.1007/s11432-020-2866-0

Efficient 16 Boolean logic and arithmetic based on bipolar oxide memristors

More info
  • ReceivedMar 15, 2020
  • AcceptedApr 8, 2020
  • PublishedAug 26, 2020

Abstract

The physically separated memory and logic units in traditional von Neumann computers place essential limits on the performance and cause increased energy consumption, and hence in-memory computing is required to overcome this bottleneck. Here, a new bipolar memristor based in-memory logic approach is proposed, which is capable of achieving all 16 possible Boolean logic functions in a single device in less than 3 steps. This approach does not require initialization and can facilitate logic cascading, and the calculation taking place in-situ is showcased by 1-bit full adder and 2-bit multiplier with improved efficiency, thus showing a great prospect in future in-memory computing architecture.


Acknowledgment

This work was supported by National Key RD Program of China (Grant No. 2017YFA0207600), National Natural Science Foundation of China (Grant Nos. 61925401, 61674006, 61927901, 61421005), and the 111 Project (Grant No. B18001). Yuchao YANG acknowledges the support from Beijing Academy of Artificial Intelligence (BAAI) and the Tencent Foundation through the Xplorer Prize.


References

[1] Waldrop M M. The chips are down for Moore's law. Nature, 2016, 530: 144-147 CrossRef ADS Google Scholar

[2] Di Ventra M, Pershin Y V. The parallel approach. Nat Phys, 2013, 9: 200-202 CrossRef ADS Google Scholar

[3] Cassinerio M, Ciocchini N, Ielmini D. Logic Computation in Phase Change Materials by Threshold and Memory Switching. Adv Mater, 2013, 25: 5975-5980 CrossRef Google Scholar

[4] Merolla P A, Arthur J V, Alvarez-Icaza R. A million spiking-neuron integrated circuit with a scalable communication network and interface. Science, 2014, 345: 668-673 CrossRef ADS Google Scholar

[5] Prezioso M, Merrikh-Bayat F, Hoskins B D. Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature, 2015, 521: 61-64 CrossRef ADS arXiv Google Scholar

[6] Li S C, Xu C, Zou Q S, et al. Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories. In: Proceedings of the 53rd Annual Design Automation Conference, Austin Texas, 2016. Google Scholar

[7] Borghetti J, Snider G S, Kuekes P J. `Memristive' switches enable `stateful' logic operations via material implication. Nature, 2010, 464: 873-876 CrossRef ADS Google Scholar

[8] Linn E, Rosezin R, Tappertzhofen S. Beyond von Neumann-logic operations in passive crossbar arrays alongside memory operations. Nanotechnology, 2012, 23: 305205 CrossRef ADS Google Scholar

[9] Yang Y, Yin M, Yu Z. Multifunctional Nanoionic Devices Enabling Simultaneous Heterosynaptic Plasticity and Efficient In-Memory Boolean Logic. Adv Electron Mater, 2017, 3: 1700032 CrossRef Google Scholar

[10] Xu L, Yuan R, Zhu Z. Memristor?Based Efficient In?Memory Logic for Cryptologic and Arithmetic Applications. Adv Mater Technol, 2019, 4: 1900212 CrossRef Google Scholar

[11] Goswami S, Matula A J, Rath S P. Robust resistive memory devices using solution-processable metal-coordinated azo aromatics. Nat Mater, 2017, 16: 1216-1224 CrossRef ADS Google Scholar

[12] Wong H S P, Salahuddin S. Memory leads the way to better computing. Nat Nanotech, 2015, 10: 191-194 CrossRef ADS Google Scholar

[13] Hwang C S. Prospective of Semiconductor Memory Devices: from Memory System to Materials. Adv Electron Mater, 2015, 1: 1400056 CrossRef Google Scholar

[14] Ma W, Zidan M A, Lu W D. Neuromorphic computing with memristive devices. Sci China Inf Sci, 2018, 61: 060422 CrossRef Google Scholar

[15] Yang Y, Huang R. Probing memristive switching in nanoionic devices. Nat Electron, 2018, 1: 274-287 CrossRef Google Scholar

[16] Yang J J, Pickett M D, Li X. Memristive switching mechanism for metal/oxide/metal nanodevices. Nat Nanotech, 2008, 3: 429-433 CrossRef Google Scholar

[17] Kim K M, Jeong D S, Hwang C S. Nanofilamentary resistive switching in binary oxide system; a review on the present status and outlook. Nanotechnology, 2011, 22: 254002 CrossRef ADS Google Scholar

[18] Choi B J, Jeong D S, Kim S K. Resistive switching mechanism of TiO$_{2}$ thin films grown by atomic-layer deposition. J Appl Phys, 2005, 98: 033715 CrossRef ADS Google Scholar

[19] Ielmini D, Wong H S P. In-memory computing with resistive switching devices. Nat Electron, 2018, 1: 333-343 CrossRef Google Scholar

[20] Vourkas I, Sirakoulis G C. Emerging Memristor-Based Logic Circuit Design Approaches: A Review. IEEE Circuits Syst Mag, 2016, 16: 15-30 CrossRef Google Scholar

[21] Li H, Gao B, Chen Z. A learnable parallel processing architecture towards unity of memory and computing. Sci Rep, 2015, 5: 13330 CrossRef ADS Google Scholar

[22] Serb A, Khiat A, Prodromakis T. Seamlessly fused digital-analogue reconfigurable computing using memristors. Nat Commun, 2018, 9: 2170 CrossRef ADS Google Scholar

[23] You T, Shuai Y, Luo W. Adv Funct Mater, 2014, 24: 3357-3365 CrossRef Google Scholar

[24] Breuer T, Siemon A, Linn E. Adv Electron Mater, 2015, 1: 1500138 CrossRef Google Scholar

[25] Siemon A, Breuer T, Aslam N. Realization of Boolean Logic Functionality Using Redox-Based Memristive Devices. Adv Funct Mater, 2015, 25: 6414-6423 CrossRef Google Scholar

[26] Gao S, Zeng F, Wang M. Implementation of Complete Boolean Logic Functions in Single Complementary Resistive Switch. Sci Rep, 2015, 5: 15467 CrossRef ADS Google Scholar

[27] Huang P, Kang J, Zhao Y. Reconfigurable Nonvolatile Logic Operations in Resistance Switching Crossbar Array for Large-Scale Circuits. Adv Mater, 2016, 28: 9758-9764 CrossRef Google Scholar

[28] Chen B, Cai F X, Zhou J T, et al. Efficient in-memory computing architecture based on crossbar arrays. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington, 2015. Google Scholar

[29] Kvatinsky S, Belousov D, Liman S. MAGIC-Memristor-Aided Logic. IEEE Trans Circuits Syst II, 2014, 61: 895-899 CrossRef Google Scholar

[30] Shen W, Huang P, Fan M. Stateful Logic Operations in One-Transistor-One- Resistor Resistive Random Access Memory Array. IEEE Electron Device Lett, 2019, 40: 1538-1541 CrossRef ADS Google Scholar

[31] Liu G, Zheng L, Wang G. A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit. IEEE Access, 2019, 7: 43691-43696 CrossRef Google Scholar

[32] Xu N, Park T G, Kim H J. A Stateful Logic Family Based on a New Logic Primitive Circuit Composed of Two Antiparallel Bipolar Memristors. Adv Intelligent Syst, 2020, 2: 1900082 CrossRef Google Scholar

[33] Hu X, Yang H, Duan S. A memristor-CMOS-based general-logic circuit and its applications. Sci Sin-Inf, 2020, 50: 289-302 CrossRef Google Scholar

[34] Wald N, Kvatinsky S. Understanding the influence of device, circuit and environmental variations on real processing in memristive memory using Memristor Aided Logic. MicroElectron J, 2019, 86: 22-33 CrossRef Google Scholar

[35] Cheng L, Zhang M Y, Li Y. Reprogrammable logic in memristive crossbar for in-memory computing. J Phys D-Appl Phys, 2017, 50: 505102 CrossRef ADS Google Scholar

[36] Kvatinsky S, Satat G, Wald N. Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies. IEEE Trans VLSI Syst, 2014, 22: 2054-2066 CrossRef Google Scholar

[37] Adam G C, Hoskins B D, Prezioso M. Optimized stateful material implication logic for three-dimensional data manipulation. Nano Res, 2016, 9: 3914-3923 CrossRef Google Scholar

[38] Chen W H, Lin W J, Lai L Y, et al. A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2017. Google Scholar

  • Figure 1

    (Color online) (a) Schematic of the Pt/Ta/Ta$_{2}$O$_{5}$/Pt/Ti device structure. (b) TEM image of the Pt/Ta/Ta$_{2}$O$_{5}$/Pt/Ti structure. Scale bar: 20 nm. (c) Typical resistive switching characteristics of the Pt/Ta/Ta$_{2}$O$_{5}$/Pt/Ti devices. (d) Current response under voltage pulse. Constant read voltage of 0.1 V was applied to the TE terminal.

  • Figure 2

    (Color online) (a) Schematic diagram of implementing three logical operations. (b) Experimental demonstration of AND, OR, and XOR in pulse measurements. The initial read operation (green background) is to know the initial resistance state and verify the correctness of the logic operation. In practical applications, only XOR logic needs to read the initial resistance state to determine the voltage input port. Constant read voltage of 0.1 V was applied to the TE terminal during the entire logic operations. $V_{\rm~set}$ added to the TE is 2.3 V, 100 ns and $V_{\rm~reset}$ added to the BE is 2.5 V, 100 ns.

  • Figure 3

    (Color online) (a) Operating sequence of the 1-bit binary full adder; (b) calculation process diagram for the typical input combination (1+1+1); (c) resistance evolution of three devices for input combination (1+1+1); (d) experimental results for all 8 possible input combinations.

  • Figure 4

    (Color online) (a) Operating sequence of the 2-bit multiplier; (b) calculation process diagram for the typical input combination (11$\times$10); (c) resistance evolution of five devices for input combination (11$\times$10); (d) experimental results for all 16 possible input combinations.

  • Table 1  

    Table 1Complete 16 Boolean logic implementations

    2*Logic
    2*InputCycle
    2*Output
    2*Logic
    2*InputCycle
    2*Output
    1212
    5*TURE$p$$q$$Z$TEBE$Z_{m}$TEBE$Z'$
    5* XOR$p$$q$$Z$TEBE$Z_{m}$TEBE$Z'$
    0010100$p$$q$00
    0110101$p$$q$01
    1010110$p$0$q$1
    1110111$p$0$q$0
    4*FALSE00010
    4* XNOR00$p$1$q$1
    0101001$p$1$q$0
    1001010$p$$q$10
    1101011$p$$q$11
    4*$p$00$p$0
    4* NAND00$p$$q$10101
    01$p$001$p$$q$10101
    10$p$110$p$$q$10101
    11$p$111$p$$q$11010
    4*$q$00010$q$00
    4* NOR00$p$$q$00101
    01010$q$0101$p$$q$01010
    10010$q$0010$p$$q$01010
    11010$q$0111$p$$q$01010
    4* NOT $p$00$p$101
    4*RIMP00$p$1$q$1
    01$p$10101$p$1$q$0
    10$p$01010$p$1$q$1
    11$p$01011$p$1$q$1
    4* NOT $q$00$p$1$q$1
    4*IMP00$q$1$p$1
    01$p$1$q$001$q$1$p$1
    10$p$0$q$110$q$1$p$0
    11$p$0$q$011$q$1$p$1
    4*AND00$p$$q$10
    4*NIMP00$p$0$q$0
    01$p$$q$1001$p$0$q$0
    10$p$$q$1010$p$0$q$1
    11$p$$q$1111$p$0$q$0
    4*OR00$p$$q$00
    4*RNIMP00$q$0$p$0
    01$p$$q$0101$q$0$p$1
    10$p$$q$0110$q$0$p$0
    11$p$$q$0111$q$0$p$0
  • Table 2  

    Table 2Comparison of XOR logic operation and 1-bit full adder schemes

    2*ReferenceXOR1-bit full adder
    Device numberStepDevice numberStep
    [7,35]46827
    [36]513629
    [37]635
    [27]44910
    [28]1610
    [10]1258
    This study1236

Copyright 2020  CHINA SCIENCE PUBLISHING & MEDIA LTD.  中国科技出版传媒股份有限公司  版权所有

京ICP备14028887号-23       京公网安备11010102003388号