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SCIENCE CHINA Physics, Mechanics & Astronomy, Volume 63 , Issue 8 : 280311(2020) https://doi.org/10.1007/s11433-020-1582-8

Efficient quantum arithmetic operation circuits for quantum image processing

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  • ReceivedFeb 10, 2020
  • AcceptedMay 20, 2020
  • PublishedJun 4, 2020
PACS numbers

Abstract

Efficient quantum circuits for arithmetic operations are vital for quantum algorithms. A fault-tolerant circuit is required for a robust quantum computing in the presence of noise. Quantum circuits based on Clifford+T gates are easily rendered fault-tolerant. Therefore, reducing the T-depth and T-Count without increasing the qubit number represents vital optimization goals for quantum circuits. In this study, we propose the fault-tolerant implementations for TR and Peres gates with optimized T-depth and T-Count. Next, we design fault-tolerant circuits for quantum arithmetic operations using the TR and Peres gates. Then, we implement cyclic and complete translations of quantum images using quantum arithmetic operations, and the scalar matrix multiplication. Comparative analysis and simulation results reveal that the proposed arithmetic and image operations are efficient. For instance, cyclic translations of a quantum image produce 50% T-depth reduction relative to the previous best-known cyclic translation.


Acknowledgment

This work was supported by the National Natural Science Foundation of China (Grant Nos. 61762012, and 61763014), the Science and Technology Project of Guangxi (Grant No. 2018JJA170083), the National Key Research and Development Plan (Grant Nos. 2018YFC1200200, and 2018YFC1200205), the Fund for Distinguished Young Scholars of Jiangxi Province (Grant No. 2018ACB2101), the Natural Science Foundation of Jiangxi Province of China (Grant No. 20192BAB207014), and the Science and Technology Research Project of Jiangxi Provincial Education Department (Grant No. GJJ190297).


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  • Figure 1

    A $2~\times~2$ binary image.

  • Figure 2

    Representations of some quantum gates, including (a) ${C_{\rm~up}}(U)$, (b) ${C_{\rm~un}}(U)$, (c) the NOT gate (i.e., $X$ gate), (d) the controlled-NOT gate (i.e., XOR gate), (e) the controlled-$V$ gate, and (f) the controlled-${V^\dag}$ gate.

  • Figure 3

    Optimal implementation circuits for (a) the Toffoli gate (T-depth 3, total depth 9), (b) the Peres gate (T-depth 4, total depth 8), (c) another Toffoli gate (T-depth 3, total depth 9), and (d) the Fredkin gate (T-depth 3, total depth 11).

  • Figure 4

    Illustration of the TR gate and its variant showing (a) the quantum symbol of $TR$1, (b) the implementation of $TR$1, (c) the quantum symbol of $TR$2, (d) the implementation of $TR$2, (e) the optimal T-depth implementation of $TR$1, (f) another optimal T-depth implementation of $TR$1, and (g) the optimal T-depth implementation of $TR$2.

  • Figure 5

    Illustration of a Peres gate $PG$1 showing (a) the quantum symbol of $PG$1, (b) the implementation of $PG$1, (c) the optimal T-depth implementation of $PG$1, and (d) another optimal T-depth implementation of $PG$1.

  • Figure 6

    Variants of the Peres gate $PG$2 and $PG$3 showing (a) the quantum symbol of $PG$2, (b) the implementation of $PG$2, (c) the optimal T-depth implementation of $PG$2, (d) the quantum symbol of $PG$3, (e) the implementation of $PG$3, (f) and the optimal T-depth implementation of $PG$3.

  • Figure 7

    The relationships between the Peres and TR gates shown by (a) $TR1*PG1$, (b) $PG1*TR1$, (c) $TR2*PG1$, and (d) $PG2*TR1$.

  • Figure 8

    (Color online) Diagram showing (a) the implementation circuit of the quantum adder, and (b) a 5-bit quantum adder.

  • Figure 9

    A 5-bit quantum modular adder.

  • Figure 10

    Illustration of a 5-bit quantum modular subtractor.

  • Figure 11

    (Color online) Diagram showing (a) quantum comparator, and (b) quantum carry circuit.

  • Figure 12

    Representation of the gate CA showing (a) the quantum symbol, (b) the implementation of CA, and (c) the optimal T-depth implementation.

  • Figure 13

    (Color online) Quantum controlled adder for $n>1$.

  • Figure 14

    (Color online) The controlled quantum modular subtractor.

  • Figure 15

    A 5-bit controlled quantum modular adder.

  • Figure 16

    Notations for the quantum arithmetic operation circuits, including (a) quantum adder, (b) quantum modular adder, (c) quantum modular subtractor, (d) controlled quantum adder, (e) controlled quantum modular adder, (f) controlled quantum modular subtractor, (g) quantum comparator, (h) quantum carry circuit, and (i) quantum multiplier. ${~+~_n}$ and ${~-~_n}$ are the symbols of the modular ${2^n}$ addition and subtraction, respectively.

  • Figure 17

    Illustration of (a) the circuit of the quantum multiplier and (b) the circuit of the quantum multiplier for $m=1$.

  • Figure 18

    (Color online) T-depth of the proposed adder and three that already exist. Note: 1 is the design by Draper et al. [27]in 2004; 2 was designed by Takahashi and Kunihiro [28]in 2008; and 3 was introduced by Takahashi et al. [29]in 2009.

  • Figure 19

    Cyclic translation of a quantum image showing (a) the cyclic right translation and (b) cyclic left translation of images.

  • Figure 20

    Simulation results of cyclic translation of a quantum image for (a) an original binary image of $32~\times~32$, (b) the cyclic right translation, and (c) the cyclic left translation.

  • Figure 21

    Local cyclic translation of a quantum image for (a) the local cyclic right translations of a quantum image, (b) the local cyclic right translations of a quantum image, and (c) combination translation.

  • Figure 22

    Simulation results for local cyclic translation of a quantum image showing (a) an original binary image of $32~\times~32$, (b) the local cyclic right translation, (c) the local cyclic left translation, and (d) the combination translation.

  • Figure 23

    Complete translation of a quantum image showing (a) the complete right translation of a quantum image and (b) the complete left translation of a quantum image.

  • Figure 24

    Simulation results of the complete translation of a quantum image for (a) an original binary image, (b) the complete right translation, and (c) the complete left translation.

  • Figure 25

    The scalar multiplication of a column vector for (a) the circuit of the scalar multiplication and (b) the simulation of the scalar multiplication.

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  • Table 1  

    Table 1Performance indicators of the gates in Figures 3-6

    Indicators Toffoli Fredkin $TR$1 $TR$2 $PG$1 $PG$2 $PG$3
    Cost 5 7 4 4 4 4 4
    Delay 5 7 4 4 4 4 4
    T-depth 3 3 3 3 3 3 3
    Total depth 9 11 9 9 9 9 9
    T-count 7 7 7 7 7 7 7
    Total count 16 18 15 15 15 15 15

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