SCIENTIA SINICA Informationis, Volume 50 , Issue 2 : 289-302(2020) https://doi.org/10.1360/N112018-00247

A memristor-CMOS-based general-logic circuit and its applications

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  • ReceivedSep 10, 2018
  • AcceptedMar 21, 2019
  • PublishedFeb 12, 2020


Memristors are a kind of information-storage device with resistance-switching dynamics. Due to the variable conductivity of memristive devices, their composite circuits can be used for implementation of logic operations. In this paper, a novel hybrid CMOS-memristor-based logic circuit is proposed for use in realizing four basic logic operations (AND, OR, XOR, XNOR) simultaneously within the same circuit. Compared with existing logic implementations (MAD Gates, MRL, IMPLY), the present circuit offers better performance and greater efficiency, owing to the significant reduction in the number of memristors used in the circuit and the power consumption. Thus, a new full-adder circuit and a binary-image-encryption circuit are designed. Unlike previous full-adder circuits, the proposed one has great advantages in terms of the number of circuit elements. In the proposed encryption circuit, there are two available encryption methods and the encryption key is independent of the circuit, which can improve the reliability of encryption results.

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  • Figure 1

    Proposed general logic circuits

  • Figure 2

    (Color online) The simulation result of proposed general logic circuit. (a) $V_{a}=~V_{L}=~``0",~V_{b}=~V_{L}=~``0"$; protectłinebreak (b) $V_{a}=~V_{L}=~``0",~V_{b}=~V_{H}=~``1"$; (c) $V_{a}=~V_{H}=~``1",~V_{b}=~V_{L}=~``0"$; (d) $V_{a}=~V_{H}=~``1",~V_{b}=~V_{H}=~``1"$

  • Figure 3

    Proposed memristor-CMOS hybrid full adder

  • Figure 4

    (Color online) The simulation results of memristor-CMOS hybrid full adder when $V_{\rm~cin}=V_{L}$. (a) $V_{A}=V_{L}$, $V_{B}=V_{L}$; (b) $V_{A}=V_{L}$, $V_{B}=V_{H}$; (c) $V_{A}=V_{H}$, $V_{B}=V_{L}$; (d) $V_{A}=V_{H}$, $V_{B}=V_{H}$

  • Figure 5

    (Color online) The simulation results of memristor-CMOS hybrid full adder when $V_{\rm~cin}=V_{L}$. (a) $V_{A}=V_{L}$, $V_{B}=V_{L}$; (b) $V_{A}=V_{L}$, $V_{B}=V_{H}$; (c) $V_{A}=V_{H}$, $V_{B}=V_{L}$; (d) $V_{A}=V_{H}$, $V_{B}=V_{H}$

  • Figure 6

    Proposed encryption cell based general logic circuit

  • Figure 7

    Proposed encryption circuit for binary image

  • Figure 8

    (Color online) Original imagematrix and key matrix. (a) Numeric “5" matrix; (b) key matrix

  • Figure 9

    (Color online) Encryption and decryption process

  • Figure 10

    Original Lena image and key

  • Figure 11

    Encryption and decryption process for Lena image

  • Table 1   Implementation process of proposed general logic circuit
    Logic Truth table Input Node voltage Output
    $a$ $b$
    AND 0 0$\to~$0 $V_{L}$ $V_{L}$ $X_1$$\to$$V_{L}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{L}$$\to$Logic“0”
    0 1$\to$0 $V_{L}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{H}$, $X_4$$\to$$V_{L}$ $V_{L}$$\to$Logic“0”
    1 0$\to$0 $V_{H}$ $V_{L}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{H}$, $X_4$$\to$$V_{L}$ $V_{L}$$\to$Logic“0”
    1 1$\to$1 $V_{H}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{H}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{H}$$\to$Logic“1”
    OR 0 0$\to$0 $V_{L}$ $V_{L}$ $X_1$$\to$$V_{L}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{L}$$\to$Logic“0”
    0 1$\to$1 $V_{L}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{H}$, $X_4$$\to$$V_{L}$ $V_{H}$$\to$Logic“1”
    1 0$\to$1 $V_{H}$ $V_{L}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{H}$, $X_4$$\to$$V_{L}$ $V_{H}$$\to$Logic“1”
    1 1$\to$1 $V_{H}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{H}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{H}$$\to$Logic“1”
    XOR 0 0$\to$0 $V_{L}$ $V_{L}$ $X_1$$\to$$V_{L}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{L}$$\to$Logic“0”
    0 1$\to$1 $V_{L}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{H}$, $X_4$$\to$$V_{L}$ $V_{H}$$\to$Logic“1”
    1 0$\to$1 $V_{H}$ $V_{L}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{H}$, $X_4$$\to$$V_{L}$ $V_{H}$$\to$Logic“1”
    1 1$\to$0 $V_{H}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{H}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{L}$$\to$Logic“0”
    XNOR 0 0$\to$1 $V_{L}$ $V_{L}$ $X_1$$\to$$V_{L}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{H}$$\to$Logic“1”
    0 1$\to$0 $V_{L}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{H}$, $X_4$$\to$$V_{L}$ $V_{L}$$\to$Logic“0”
    1 0$\to$0 $V_{H}$ $V_{L}$ $X_1\to~V_{H}$, $X_2\to~V_{L}$, $X_3\to~V_{H}$, $X_4\to~V_{L}$ $V_{L}\to$Logic“0”
    1 1$\to$1 $V_{H}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{H}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{H}$$\to$Logic“1”
  • Table 2   Several logic circuits' performance for implementation of AND-OR-XOR-XNOR logic
    Logic circuits Components Generalized Power estimation Circuit design constraints Cascading
    Proposed general 4 memristors Excellent 1.592 mW Low Excellent
    logic circuit 4 MOSFETs
    13 memristors
    MAD Gates 13 resistors Normal 4.306 mW High Normal
    7 switches
    MRL 16 memristors Normal 6.312 mW Low Excellent
    10 MOSFETs
    IMPLY 18 memristors Normal 12.490 mW High Normal
    4 resistors
    Hybrid CMOS 8 memristors Good 3.183 mW Low Excellent
    4 MOSFETs
  • Table 3   The truth table of full adder
    Carry voltage Input Output
    $V_{A}$ $V_{B}$
    $V_{\rm~cin}~\to~V_{L}$ $V_{L}$ $V_{L}$ $V_{\rm~sum}$ $\to$ $V_{L}$, $V_{\rm~cout}$ $\to$ $V_{L}$
    $V_{L}$ $V_{H}$ $V_{\rm~sum}$ $\to$ $V_{H}$, $V_{\rm~cout}$ $\to$ $V_{L}$
    $V_{H}$ $V_{L}$ $V_{\rm~sum}$ $\to$ $V_{H}$, $V_{\rm~cout}$ $\to$ $V_{L}$
    $V_{H}$ $V_{H}$ $V_{\rm~sum}$ $\to$ $V_{L}$, $V_{\rm~cout}$ $\to$ $V_{H}$
    $V_{\rm~cin}$ $\to$ $V_{H}$ $V_{L}$ $V_{L}$ $V_{\rm~sum}$ $\to$ $V_{H}$, $V_{\rm~cout}$ $\to$ $V_{L}$
    $V_{L}$ $V_{H}$ $V_{\rm~sum}$ $\to$ $V_{L}$, $V_{\rm~cout}$ $\to$ $V_{H}$
    $V_{H}$ $V_{L}$ $V_{\rm~sum}$ $\to$ $V_{L}$, $V_{\rm~cout}$ $\to$ $V_{H}$
    $V_{H}$ $V_{H}$ $V_{\rm~sum}$ $\to$ $V_{H}$, $V_{\rm~cout}$ $\to$ $V_{H}$
  • Table 4   Comparison of the components required by the proposed circuits and prior work for $N$-bit adder
    MAD Gates MRL IMPLY Proposed general logic circuit
    Components $8N$ memristors $18N$ memristors $7N+1$ memristors $4N~$ memristors
    $2N+3$ drivers $3N$ drivers $7N$ drivers $2N+1$ drivers
    $9N$ resistors $4N$ MOSFETs $~N$ resistors $8N$ MOSFETs
    $14N$ switches $8N-1$ switches

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